crypto: ux500/cryp - delete driver (453de3eb) · Commits · EulixOS / Software / Kernel

drivers/crypto/ux500/Kconfig

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		# Author: Shujuan Chen (shujuan.chen@stericsson.com)
		#

		config CRYPTO_DEV_UX500_CRYP
		tristate "UX500 crypto driver for CRYP block"
		depends on CRYPTO_DEV_UX500
		select CRYPTO_ALGAPI
		select CRYPTO_SKCIPHER
		select CRYPTO_LIB_DES
		help
		This selects the crypto driver for the UX500_CRYP hardware. It supports
		AES-ECB, CBC and CTR with keys sizes of 128, 192 and 256 bit sizes.

		config CRYPTO_DEV_UX500_HASH
		tristate "UX500 crypto driver for HASH block"
		depends on CRYPTO_DEV_UX500

drivers/crypto/ux500/Makefile

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		@@ -5,4 +5,3 @@
		#

		obj-$(CONFIG_CRYPTO_DEV_UX500_HASH) += hash/
		obj-$(CONFIG_CRYPTO_DEV_UX500_CRYP) += cryp/

drivers/crypto/ux500/cryp/Makefile

deleted100644 → 0

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		# SPDX-License-Identifier: GPL-2.0-only
		#/*
		# * Copyright (C) ST-Ericsson SA 2010
		# * Author: shujuan.chen@stericsson.com for ST-Ericsson.
		# */

		ccflags-$(CONFIG_CRYPTO_DEV_UX500_DEBUG) += -DDEBUG

		obj-$(CONFIG_CRYPTO_DEV_UX500_CRYP) += ux500_cryp.o
		ux500_cryp-objs := cryp.o cryp_irq.o cryp_core.o

drivers/crypto/ux500/cryp/cryp.c

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		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (C) ST-Ericsson SA 2010
		* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
		* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
		* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
		* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
		* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
		*/

		#include <linux/errno.h>
		#include <linux/kernel.h>
		#include <linux/types.h>

		#include "cryp_p.h"
		#include "cryp.h"

		/*
		* cryp_wait_until_done - wait until the device logic is not busy
		*/
		void cryp_wait_until_done(struct cryp_device_data *device_data)
		{
		while (cryp_is_logic_busy(device_data))
		cpu_relax();
		}

		/**
		* cryp_check - This routine checks Peripheral and PCell Id
		* @device_data: Pointer to the device data struct for base address.
		*/
		int cryp_check(struct cryp_device_data *device_data)
		{
		int peripheralid2 = 0;

		if (NULL == device_data)
		return -EINVAL;

		peripheralid2 = readl_relaxed(&device_data->base->periphId2);

		if (peripheralid2 != CRYP_PERIPHERAL_ID2_DB8500)
		return -EPERM;

		/* Check Peripheral and Pcell Id Register for CRYP */
		if ((CRYP_PERIPHERAL_ID0 ==
		readl_relaxed(&device_data->base->periphId0))
		&& (CRYP_PERIPHERAL_ID1 ==
		readl_relaxed(&device_data->base->periphId1))
		&& (CRYP_PERIPHERAL_ID3 ==
		readl_relaxed(&device_data->base->periphId3))
		&& (CRYP_PCELL_ID0 ==
		readl_relaxed(&device_data->base->pcellId0))
		&& (CRYP_PCELL_ID1 ==
		readl_relaxed(&device_data->base->pcellId1))
		&& (CRYP_PCELL_ID2 ==
		readl_relaxed(&device_data->base->pcellId2))
		&& (CRYP_PCELL_ID3 ==
		readl_relaxed(&device_data->base->pcellId3))) {
		return 0;
		}

		return -EPERM;
		}

		/**
		* cryp_activity - This routine enables/disable the cryptography function.
		* @device_data: Pointer to the device data struct for base address.
		* @cryp_crypen: Enable/Disable functionality
		*/
		void cryp_activity(struct cryp_device_data *device_data,
		enum cryp_crypen cryp_crypen)
		{
		CRYP_PUT_BITS(&device_data->base->cr,
		cryp_crypen,
		CRYP_CR_CRYPEN_POS,
		CRYP_CR_CRYPEN_MASK);
		}

		/**
		* cryp_flush_inoutfifo - Resets both the input and the output FIFOs
		* @device_data: Pointer to the device data struct for base address.
		*/
		void cryp_flush_inoutfifo(struct cryp_device_data *device_data)
		{
		/*
		* We always need to disable the hardware before trying to flush the
		* FIFO. This is something that isn't written in the design
		* specification, but we have been informed by the hardware designers
		* that this must be done.
		*/
		cryp_activity(device_data, CRYP_CRYPEN_DISABLE);
		cryp_wait_until_done(device_data);

		CRYP_SET_BITS(&device_data->base->cr, CRYP_CR_FFLUSH_MASK);
		/*
		* CRYP_SR_INFIFO_READY_MASK is the expected value on the status
		* register when starting a new calculation, which means Input FIFO is
		* not full and input FIFO is empty.
		*/
		while (readl_relaxed(&device_data->base->sr) !=
		CRYP_SR_INFIFO_READY_MASK)
		cpu_relax();
		}

		/**
		* cryp_set_configuration - This routine set the cr CRYP IP
		* @device_data: Pointer to the device data struct for base address.
		* @cryp_config: Pointer to the configuration parameter
		* @control_register: The control register to be written later on.
		*/
		int cryp_set_configuration(struct cryp_device_data *device_data,
		struct cryp_config *cryp_config,
		u32 *control_register)
		{
		u32 cr_for_kse;

		if (NULL == device_data \|\| NULL == cryp_config)
		return -EINVAL;

		*control_register \|= (cryp_config->keysize << CRYP_CR_KEYSIZE_POS);

		/* Prepare key for decryption in AES_ECB and AES_CBC mode. */
		if ((CRYP_ALGORITHM_DECRYPT == cryp_config->algodir) &&
		((CRYP_ALGO_AES_ECB == cryp_config->algomode) \|\|
		(CRYP_ALGO_AES_CBC == cryp_config->algomode))) {
		cr_for_kse = *control_register;
		/*
		* This seems a bit odd, but it is indeed needed to set this to
		* encrypt even though it is a decryption that we are doing. It
		* also mentioned in the design spec that you need to do this.
		* After the keyprepartion for decrypting is done you should set
		* algodir back to decryption, which is done outside this if
		* statement.
		*
		* According to design specification we should set mode ECB
		* during key preparation even though we might be running CBC
		* when enter this function.
		*
		* Writing to KSE_ENABLED will drop CRYPEN when key preparation
		* is done. Therefore we need to set CRYPEN again outside this
		* if statement when running decryption.
		*/
		cr_for_kse \|= ((CRYP_ALGORITHM_ENCRYPT << CRYP_CR_ALGODIR_POS) \|
		(CRYP_ALGO_AES_ECB << CRYP_CR_ALGOMODE_POS) \|
		(CRYP_CRYPEN_ENABLE << CRYP_CR_CRYPEN_POS) \|
		(KSE_ENABLED << CRYP_CR_KSE_POS));

		writel_relaxed(cr_for_kse, &device_data->base->cr);
		cryp_wait_until_done(device_data);
		}

		*control_register \|=
		((cryp_config->algomode << CRYP_CR_ALGOMODE_POS) \|
		(cryp_config->algodir << CRYP_CR_ALGODIR_POS));

		return 0;
		}

		/**
		* cryp_configure_protection - set the protection bits in the CRYP logic.
		* @device_data: Pointer to the device data struct for base address.
		* @p_protect_config: Pointer to the protection mode and
		* secure mode configuration
		*/
		int cryp_configure_protection(struct cryp_device_data *device_data,
		struct cryp_protection_config *p_protect_config)
		{
		if (NULL == p_protect_config)
		return -EINVAL;

		CRYP_WRITE_BIT(&device_data->base->cr,
		(u32) p_protect_config->secure_access,
		CRYP_CR_SECURE_MASK);
		CRYP_PUT_BITS(&device_data->base->cr,
		p_protect_config->privilege_access,
		CRYP_CR_PRLG_POS,
		CRYP_CR_PRLG_MASK);

		return 0;
		}

		/**
		* cryp_is_logic_busy - returns the busy status of the CRYP logic
		* @device_data: Pointer to the device data struct for base address.
		*/
		int cryp_is_logic_busy(struct cryp_device_data *device_data)
		{
		return CRYP_TEST_BITS(&device_data->base->sr,
		CRYP_SR_BUSY_MASK);
		}

		/**
		* cryp_configure_for_dma - configures the CRYP IP for DMA operation
		* @device_data: Pointer to the device data struct for base address.
		* @dma_req: Specifies the DMA request type value.
		*/
		void cryp_configure_for_dma(struct cryp_device_data *device_data,
		enum cryp_dma_req_type dma_req)
		{
		CRYP_SET_BITS(&device_data->base->dmacr,
		(u32) dma_req);
		}

		/**
		* cryp_configure_key_values - configures the key values for CRYP operations
		* @device_data: Pointer to the device data struct for base address.
		* @key_reg_index: Key value index register
		* @key_value: The key value struct
		*/
		int cryp_configure_key_values(struct cryp_device_data *device_data,
		enum cryp_key_reg_index key_reg_index,
		struct cryp_key_value key_value)
		{
		while (cryp_is_logic_busy(device_data))
		cpu_relax();

		switch (key_reg_index) {
		case CRYP_KEY_REG_1:
		writel_relaxed(key_value.key_value_left,
		&device_data->base->key_1_l);
		writel_relaxed(key_value.key_value_right,
		&device_data->base->key_1_r);
		break;
		case CRYP_KEY_REG_2:
		writel_relaxed(key_value.key_value_left,
		&device_data->base->key_2_l);
		writel_relaxed(key_value.key_value_right,
		&device_data->base->key_2_r);
		break;
		case CRYP_KEY_REG_3:
		writel_relaxed(key_value.key_value_left,
		&device_data->base->key_3_l);
		writel_relaxed(key_value.key_value_right,
		&device_data->base->key_3_r);
		break;
		case CRYP_KEY_REG_4:
		writel_relaxed(key_value.key_value_left,
		&device_data->base->key_4_l);
		writel_relaxed(key_value.key_value_right,
		&device_data->base->key_4_r);
		break;
		default:
		return -EINVAL;
		}

		return 0;
		}

		/**
		* cryp_configure_init_vector - configures the initialization vector register
		* @device_data: Pointer to the device data struct for base address.
		* @init_vector_index: Specifies the index of the init vector.
		* @init_vector_value: Specifies the value for the init vector.
		*/
		int cryp_configure_init_vector(struct cryp_device_data *device_data,
		enum cryp_init_vector_index
		init_vector_index,
		struct cryp_init_vector_value
		init_vector_value)
		{
		while (cryp_is_logic_busy(device_data))
		cpu_relax();

		switch (init_vector_index) {
		case CRYP_INIT_VECTOR_INDEX_0:
		writel_relaxed(init_vector_value.init_value_left,
		&device_data->base->init_vect_0_l);
		writel_relaxed(init_vector_value.init_value_right,
		&device_data->base->init_vect_0_r);
		break;
		case CRYP_INIT_VECTOR_INDEX_1:
		writel_relaxed(init_vector_value.init_value_left,
		&device_data->base->init_vect_1_l);
		writel_relaxed(init_vector_value.init_value_right,
		&device_data->base->init_vect_1_r);
		break;
		default:
		return -EINVAL;
		}

		return 0;
		}

		/**
		* cryp_save_device_context - Store hardware registers and
		* other device context parameter
		* @device_data: Pointer to the device data struct for base address.
		* @ctx: Crypto device context
		* @cryp_mode: Mode: Polling, Interrupt or DMA
		*/
		void cryp_save_device_context(struct cryp_device_data *device_data,
		struct cryp_device_context *ctx,
		int cryp_mode)
		{
		enum cryp_algo_mode algomode;
		struct cryp_register __iomem *src_reg = device_data->base;
		struct cryp_config *config =
		(struct cryp_config *)device_data->current_ctx;

		/*
		* Always start by disable the hardware and wait for it to finish the
		* ongoing calculations before trying to reprogram it.
		*/
		cryp_activity(device_data, CRYP_CRYPEN_DISABLE);
		cryp_wait_until_done(device_data);

		if (cryp_mode == CRYP_MODE_DMA)
		cryp_configure_for_dma(device_data, CRYP_DMA_DISABLE_BOTH);

		if (CRYP_TEST_BITS(&src_reg->sr, CRYP_SR_IFEM_MASK) == 0)
		ctx->din = readl_relaxed(&src_reg->din);

		ctx->cr = readl_relaxed(&src_reg->cr) & CRYP_CR_CONTEXT_SAVE_MASK;

		switch (config->keysize) {
		case CRYP_KEY_SIZE_256:
		ctx->key_4_l = readl_relaxed(&src_reg->key_4_l);
		ctx->key_4_r = readl_relaxed(&src_reg->key_4_r);
		fallthrough;

		case CRYP_KEY_SIZE_192:
		ctx->key_3_l = readl_relaxed(&src_reg->key_3_l);
		ctx->key_3_r = readl_relaxed(&src_reg->key_3_r);
		fallthrough;

		case CRYP_KEY_SIZE_128:
		ctx->key_2_l = readl_relaxed(&src_reg->key_2_l);
		ctx->key_2_r = readl_relaxed(&src_reg->key_2_r);
		fallthrough;

		default:
		ctx->key_1_l = readl_relaxed(&src_reg->key_1_l);
		ctx->key_1_r = readl_relaxed(&src_reg->key_1_r);
		}

		/* Save IV for CBC mode for both AES and DES. */
		algomode = ((ctx->cr & CRYP_CR_ALGOMODE_MASK) >> CRYP_CR_ALGOMODE_POS);
		if (algomode == CRYP_ALGO_TDES_CBC \|\|
		algomode == CRYP_ALGO_DES_CBC \|\|
		algomode == CRYP_ALGO_AES_CBC) {
		ctx->init_vect_0_l = readl_relaxed(&src_reg->init_vect_0_l);
		ctx->init_vect_0_r = readl_relaxed(&src_reg->init_vect_0_r);
		ctx->init_vect_1_l = readl_relaxed(&src_reg->init_vect_1_l);
		ctx->init_vect_1_r = readl_relaxed(&src_reg->init_vect_1_r);
		}
		}

		/**
		* cryp_restore_device_context - Restore hardware registers and
		* other device context parameter
		* @device_data: Pointer to the device data struct for base address.
		* @ctx: Crypto device context
		*/
		void cryp_restore_device_context(struct cryp_device_data *device_data,
		struct cryp_device_context *ctx)
		{
		struct cryp_register __iomem *reg = device_data->base;
		struct cryp_config *config =
		(struct cryp_config *)device_data->current_ctx;

		/*
		* Fall through for all items in switch statement. DES is captured in
		* the default.
		*/
		switch (config->keysize) {
		case CRYP_KEY_SIZE_256:
		writel_relaxed(ctx->key_4_l, &reg->key_4_l);
		writel_relaxed(ctx->key_4_r, &reg->key_4_r);
		fallthrough;

		case CRYP_KEY_SIZE_192:
		writel_relaxed(ctx->key_3_l, &reg->key_3_l);
		writel_relaxed(ctx->key_3_r, &reg->key_3_r);
		fallthrough;

		case CRYP_KEY_SIZE_128:
		writel_relaxed(ctx->key_2_l, &reg->key_2_l);
		writel_relaxed(ctx->key_2_r, &reg->key_2_r);
		fallthrough;

		default:
		writel_relaxed(ctx->key_1_l, &reg->key_1_l);
		writel_relaxed(ctx->key_1_r, &reg->key_1_r);
		}

		/* Restore IV for CBC mode for AES and DES. */
		if (config->algomode == CRYP_ALGO_TDES_CBC \|\|
		config->algomode == CRYP_ALGO_DES_CBC \|\|
		config->algomode == CRYP_ALGO_AES_CBC) {
		writel_relaxed(ctx->init_vect_0_l, &reg->init_vect_0_l);
		writel_relaxed(ctx->init_vect_0_r, &reg->init_vect_0_r);
		writel_relaxed(ctx->init_vect_1_l, &reg->init_vect_1_l);
		writel_relaxed(ctx->init_vect_1_r, &reg->init_vect_1_r);
		}
		}

drivers/crypto/ux500/cryp/cryp.h

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		/* SPDX-License-Identifier: GPL-2.0-only */
		/*
		* Copyright (C) ST-Ericsson SA 2010
		* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
		* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
		* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
		* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
		* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
		*/

		#ifndef _CRYP_H_
		#define _CRYP_H_

		#include <linux/completion.h>
		#include <linux/dmaengine.h>
		#include <linux/klist.h>
		#include <linux/mutex.h>

		#define DEV_DBG_NAME "crypX crypX:"

		/* CRYP enable/disable */
		enum cryp_crypen {
		CRYP_CRYPEN_DISABLE = 0,
		CRYP_CRYPEN_ENABLE = 1
		};

		/* CRYP Start Computation enable/disable */
		enum cryp_start {
		CRYP_START_DISABLE = 0,
		CRYP_START_ENABLE = 1
		};

		/* CRYP Init Signal enable/disable */
		enum cryp_init {
		CRYP_INIT_DISABLE = 0,
		CRYP_INIT_ENABLE = 1
		};

		/* Cryp State enable/disable */
		enum cryp_state {
		CRYP_STATE_DISABLE = 0,
		CRYP_STATE_ENABLE = 1
		};

		/* Key preparation bit enable */
		enum cryp_key_prep {
		KSE_DISABLED = 0,
		KSE_ENABLED = 1
		};

		/* Key size for AES */
		#define CRYP_KEY_SIZE_128 (0)
		#define CRYP_KEY_SIZE_192 (1)
		#define CRYP_KEY_SIZE_256 (2)

		/* AES modes */
		enum cryp_algo_mode {
		CRYP_ALGO_TDES_ECB,
		CRYP_ALGO_TDES_CBC,
		CRYP_ALGO_DES_ECB,
		CRYP_ALGO_DES_CBC,
		CRYP_ALGO_AES_ECB,
		CRYP_ALGO_AES_CBC,
		CRYP_ALGO_AES_CTR,
		CRYP_ALGO_AES_XTS
		};

		/* Cryp Encryption or Decryption */
		enum cryp_algorithm_dir {
		CRYP_ALGORITHM_ENCRYPT,
		CRYP_ALGORITHM_DECRYPT
		};

		/* Hardware access method */
		enum cryp_mode {
		CRYP_MODE_POLLING,
		CRYP_MODE_INTERRUPT,
		CRYP_MODE_DMA
		};

		/**
		* struct cryp_config -
		* @keysize: Key size for AES
		* @algomode: AES modes
		* @algodir: Cryp Encryption or Decryption
		*
		* CRYP configuration structure to be passed to set configuration
		*/
		struct cryp_config {
		int keysize;
		enum cryp_algo_mode algomode;
		enum cryp_algorithm_dir algodir;
		};

		/**
		* struct cryp_protection_config -
		* @privilege_access: Privileged cryp state enable/disable
		* @secure_access: Secure cryp state enable/disable
		*
		* Protection configuration structure for setting privilage access
		*/
		struct cryp_protection_config {
		enum cryp_state privilege_access;
		enum cryp_state secure_access;
		};

		/* Cryp status */
		enum cryp_status_id {
		CRYP_STATUS_BUSY = 0x10,
		CRYP_STATUS_OUTPUT_FIFO_FULL = 0x08,
		CRYP_STATUS_OUTPUT_FIFO_NOT_EMPTY = 0x04,
		CRYP_STATUS_INPUT_FIFO_NOT_FULL = 0x02,
		CRYP_STATUS_INPUT_FIFO_EMPTY = 0x01
		};

		/* Cryp DMA interface */
		#define CRYP_DMA_TX_FIFO 0x08
		#define CRYP_DMA_RX_FIFO 0x10

		enum cryp_dma_req_type {
		CRYP_DMA_DISABLE_BOTH,
		CRYP_DMA_ENABLE_IN_DATA,
		CRYP_DMA_ENABLE_OUT_DATA,
		CRYP_DMA_ENABLE_BOTH_DIRECTIONS
		};

		enum cryp_dma_channel {
		CRYP_DMA_RX = 0,
		CRYP_DMA_TX
		};

		/* Key registers */
		enum cryp_key_reg_index {
		CRYP_KEY_REG_1,
		CRYP_KEY_REG_2,
		CRYP_KEY_REG_3,
		CRYP_KEY_REG_4
		};

		/* Key register left and right */
		struct cryp_key_value {
		u32 key_value_left;
		u32 key_value_right;
		};

		/* Cryp Initialization structure */
		enum cryp_init_vector_index {
		CRYP_INIT_VECTOR_INDEX_0,
		CRYP_INIT_VECTOR_INDEX_1
		};

		/* struct cryp_init_vector_value -
		* @init_value_left
		* @init_value_right
		* */
		struct cryp_init_vector_value {
		u32 init_value_left;
		u32 init_value_right;
		};

		/**
		* struct cryp_device_context - structure for a cryp context.
		* @cr: control register
		* @dmacr: DMA control register
		* @imsc: Interrupt mask set/clear register
		* @key_1_l: Key 1l register
		* @key_1_r: Key 1r register
		* @key_2_l: Key 2l register
		* @key_2_r: Key 2r register
		* @key_3_l: Key 3l register
		* @key_3_r: Key 3r register
		* @key_4_l: Key 4l register
		* @key_4_r: Key 4r register
		* @init_vect_0_l: Initialization vector 0l register
		* @init_vect_0_r: Initialization vector 0r register
		* @init_vect_1_l: Initialization vector 1l register
		* @init_vect_1_r: Initialization vector 0r register
		* @din: Data in register
		* @dout: Data out register
		*
		* CRYP power management specifc structure.
		*/
		struct cryp_device_context {
		u32 cr;
		u32 dmacr;
		u32 imsc;

		u32 key_1_l;
		u32 key_1_r;
		u32 key_2_l;
		u32 key_2_r;
		u32 key_3_l;
		u32 key_3_r;
		u32 key_4_l;
		u32 key_4_r;

		u32 init_vect_0_l;
		u32 init_vect_0_r;
		u32 init_vect_1_l;
		u32 init_vect_1_r;

		u32 din;
		u32 dout;
		};

		struct cryp_dma {
		dma_cap_mask_t mask;
		struct completion cryp_dma_complete;
		struct dma_chan *chan_cryp2mem;
		struct dma_chan *chan_mem2cryp;
		struct stedma40_chan_cfg *cfg_cryp2mem;
		struct stedma40_chan_cfg *cfg_mem2cryp;
		int sg_src_len;
		int sg_dst_len;
		struct scatterlist *sg_src;
		struct scatterlist *sg_dst;
		int nents_src;
		int nents_dst;
		};

		/**
		* struct cryp_device_data - structure for a cryp device.
		* @base: Pointer to virtual base address of the cryp device.
		* @phybase: Pointer to physical memory location of the cryp device.
		* @dev: Pointer to the devices dev structure.
		* @clk: Pointer to the device's clock control.
		* @irq: IRQ number
		* @pwr_regulator: Pointer to the device's power control.
		* @power_status: Current status of the power.
		* @ctx_lock: Lock for current_ctx.
		* @current_ctx: Pointer to the currently allocated context.
		* @list_node: For inclusion into a klist.
		* @dma: The dma structure holding channel configuration.
		* @power_state: TRUE = power state on, FALSE = power state off.
		* @power_state_spinlock: Spinlock for power_state.
		* @restore_dev_ctx: TRUE = saved ctx, FALSE = no saved ctx.
		*/
		struct cryp_device_data {
		struct cryp_register __iomem *base;
		phys_addr_t phybase;
		struct device *dev;
		struct clk *clk;
		int irq;
		struct regulator *pwr_regulator;
		int power_status;
		spinlock_t ctx_lock;
		struct cryp_ctx *current_ctx;
		struct klist_node list_node;
		struct cryp_dma dma;
		bool power_state;
		spinlock_t power_state_spinlock;
		bool restore_dev_ctx;
		};

		void cryp_wait_until_done(struct cryp_device_data *device_data);

		/* Initialization functions */

		int cryp_check(struct cryp_device_data *device_data);

		void cryp_activity(struct cryp_device_data *device_data,
		enum cryp_crypen cryp_crypen);

		void cryp_flush_inoutfifo(struct cryp_device_data *device_data);

		int cryp_set_configuration(struct cryp_device_data *device_data,
		struct cryp_config *cryp_config,
		u32 *control_register);

		void cryp_configure_for_dma(struct cryp_device_data *device_data,
		enum cryp_dma_req_type dma_req);

		int cryp_configure_key_values(struct cryp_device_data *device_data,
		enum cryp_key_reg_index key_reg_index,
		struct cryp_key_value key_value);

		int cryp_configure_init_vector(struct cryp_device_data *device_data,
		enum cryp_init_vector_index
		init_vector_index,
		struct cryp_init_vector_value
		init_vector_value);

		int cryp_configure_protection(struct cryp_device_data *device_data,
		struct cryp_protection_config *p_protect_config);

		/* Power management funtions */
		void cryp_save_device_context(struct cryp_device_data *device_data,
		struct cryp_device_context *ctx,
		int cryp_mode);

		void cryp_restore_device_context(struct cryp_device_data *device_data,
		struct cryp_device_context *ctx);

		/* Data transfer and status bits. */
		int cryp_is_logic_busy(struct cryp_device_data *device_data);

		int cryp_get_status(struct cryp_device_data *device_data);

		/**
		* cryp_write_indata - This routine writes 32 bit data into the data input
		* register of the cryptography IP.
		* @device_data: Pointer to the device data struct for base address.
		* @write_data: Data to write.
		*/
		int cryp_write_indata(struct cryp_device_data *device_data, u32 write_data);

		/**
		* cryp_read_outdata - This routine reads the data from the data output
		* register of the CRYP logic
		* @device_data: Pointer to the device data struct for base address.
		* @read_data: Read the data from the output FIFO.
		*/
		int cryp_read_outdata(struct cryp_device_data device_data, u32 read_data);

		#endif /* _CRYP_H_ */