Loading arch/blackfin/kernel/bfin_dma_5xx.c +26 −0 Original line number Diff line number Diff line Loading @@ -420,6 +420,32 @@ unsigned short get_dma_curr_ycount(unsigned int channel) } EXPORT_SYMBOL(get_dma_curr_ycount); unsigned long get_dma_next_desc_ptr(unsigned int channel) { BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE && channel < MAX_BLACKFIN_DMA_CHANNEL)); return dma_ch[channel].regs->next_desc_ptr; } EXPORT_SYMBOL(get_dma_next_desc_ptr); unsigned long get_dma_curr_desc_ptr(unsigned int channel) { BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE && channel < MAX_BLACKFIN_DMA_CHANNEL)); return dma_ch[channel].regs->curr_desc_ptr; } unsigned long get_dma_curr_addr(unsigned int channel) { BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE && channel < MAX_BLACKFIN_DMA_CHANNEL)); return dma_ch[channel].regs->curr_addr_ptr; } EXPORT_SYMBOL(get_dma_curr_addr); static void *__dma_memcpy(void *dest, const void *src, size_t size) { int direction; /* 1 - address decrease, 0 - address increase */ Loading arch/blackfin/mach-bf548/dma.c +1 −0 Original line number Diff line number Diff line Loading @@ -64,6 +64,7 @@ (struct dma_register *) MDMA_D3_NEXT_DESC_PTR, (struct dma_register *) MDMA_S3_NEXT_DESC_PTR, }; EXPORT_SYMBOL(base_addr); int channel2irq(unsigned int channel) { Loading include/asm-blackfin/dma.h +4 −3 Original line number Diff line number Diff line Loading @@ -109,9 +109,7 @@ struct dma_register { unsigned long curr_desc_ptr; /* DMA Current Descriptor Pointer register */ unsigned short curr_addr_ptr_lo; /* DMA Current Address Pointer register */ unsigned short curr_addr_ptr_hi; /* DMA Current Address Pointer unsigned long curr_addr_ptr; /* DMA Current Address Pointer register */ unsigned short irq_status; /* DMA irq status register */ unsigned short dummy6; Loading Loading @@ -166,6 +164,9 @@ void set_dma_curr_addr(unsigned int channel, unsigned long addr); unsigned short get_dma_curr_irqstat(unsigned int channel); unsigned short get_dma_curr_xcount(unsigned int channel); unsigned short get_dma_curr_ycount(unsigned int channel); unsigned long get_dma_next_desc_ptr(unsigned int channel); unsigned long get_dma_curr_desc_ptr(unsigned int channel); unsigned long get_dma_curr_addr(unsigned int channel); /* set large DMA mode descriptor */ void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg); Loading include/asm-blackfin/mach-bf548/defBF549.h +1 −1 Original line number Diff line number Diff line Loading @@ -1178,7 +1178,7 @@ /* Bit masks for HOST_STATUS */ #define READY 0x1 /* DMA Ready */ #define DMA_READY 0x1 /* DMA Ready */ #define FIFOFULL 0x2 /* FIFO Full */ #define FIFOEMPTY 0x4 /* FIFO Empty */ #define DMA_COMPLETE 0x8 /* DMA Complete */ Loading include/asm-blackfin/mach-bf548/defBF54x_base.h +1 −1 Original line number Diff line number Diff line Loading @@ -3303,7 +3303,7 @@ #define MFD 0xf000 /* Multi channel Frame Delay */ #define FSDR 0x80 /* Frame Sync to Data Relationship */ #define MCMEM 0x10 /* Multi channel Frame Mode Enable */ #define MCMEN 0x10 /* Multi channel Frame Mode Enable */ #define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */ #define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */ #define MCCRM 0x3 /* 2X Clock Recovery Mode */ Loading Loading
arch/blackfin/kernel/bfin_dma_5xx.c +26 −0 Original line number Diff line number Diff line Loading @@ -420,6 +420,32 @@ unsigned short get_dma_curr_ycount(unsigned int channel) } EXPORT_SYMBOL(get_dma_curr_ycount); unsigned long get_dma_next_desc_ptr(unsigned int channel) { BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE && channel < MAX_BLACKFIN_DMA_CHANNEL)); return dma_ch[channel].regs->next_desc_ptr; } EXPORT_SYMBOL(get_dma_next_desc_ptr); unsigned long get_dma_curr_desc_ptr(unsigned int channel) { BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE && channel < MAX_BLACKFIN_DMA_CHANNEL)); return dma_ch[channel].regs->curr_desc_ptr; } unsigned long get_dma_curr_addr(unsigned int channel) { BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE && channel < MAX_BLACKFIN_DMA_CHANNEL)); return dma_ch[channel].regs->curr_addr_ptr; } EXPORT_SYMBOL(get_dma_curr_addr); static void *__dma_memcpy(void *dest, const void *src, size_t size) { int direction; /* 1 - address decrease, 0 - address increase */ Loading
arch/blackfin/mach-bf548/dma.c +1 −0 Original line number Diff line number Diff line Loading @@ -64,6 +64,7 @@ (struct dma_register *) MDMA_D3_NEXT_DESC_PTR, (struct dma_register *) MDMA_S3_NEXT_DESC_PTR, }; EXPORT_SYMBOL(base_addr); int channel2irq(unsigned int channel) { Loading
include/asm-blackfin/dma.h +4 −3 Original line number Diff line number Diff line Loading @@ -109,9 +109,7 @@ struct dma_register { unsigned long curr_desc_ptr; /* DMA Current Descriptor Pointer register */ unsigned short curr_addr_ptr_lo; /* DMA Current Address Pointer register */ unsigned short curr_addr_ptr_hi; /* DMA Current Address Pointer unsigned long curr_addr_ptr; /* DMA Current Address Pointer register */ unsigned short irq_status; /* DMA irq status register */ unsigned short dummy6; Loading Loading @@ -166,6 +164,9 @@ void set_dma_curr_addr(unsigned int channel, unsigned long addr); unsigned short get_dma_curr_irqstat(unsigned int channel); unsigned short get_dma_curr_xcount(unsigned int channel); unsigned short get_dma_curr_ycount(unsigned int channel); unsigned long get_dma_next_desc_ptr(unsigned int channel); unsigned long get_dma_curr_desc_ptr(unsigned int channel); unsigned long get_dma_curr_addr(unsigned int channel); /* set large DMA mode descriptor */ void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg); Loading
include/asm-blackfin/mach-bf548/defBF549.h +1 −1 Original line number Diff line number Diff line Loading @@ -1178,7 +1178,7 @@ /* Bit masks for HOST_STATUS */ #define READY 0x1 /* DMA Ready */ #define DMA_READY 0x1 /* DMA Ready */ #define FIFOFULL 0x2 /* FIFO Full */ #define FIFOEMPTY 0x4 /* FIFO Empty */ #define DMA_COMPLETE 0x8 /* DMA Complete */ Loading
include/asm-blackfin/mach-bf548/defBF54x_base.h +1 −1 Original line number Diff line number Diff line Loading @@ -3303,7 +3303,7 @@ #define MFD 0xf000 /* Multi channel Frame Delay */ #define FSDR 0x80 /* Frame Sync to Data Relationship */ #define MCMEM 0x10 /* Multi channel Frame Mode Enable */ #define MCMEN 0x10 /* Multi channel Frame Mode Enable */ #define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */ #define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */ #define MCCRM 0x3 /* 2X Clock Recovery Mode */ Loading