Commit 450405cd authored by Rodrigo Vivi's avatar Rodrigo Vivi
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Merge tag 'gvt-fixes-2021-07-15' of https://github.com/intel/gvt-linux into drm-intel-fixes 



gvt-fixes-2021-07-15

- Fix shadow ppgtt invalidation with proper D3 state tracking (Colin)

Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715022237.GX12150@zhen-hp.sh.intel.com
parents 2734d6c1 c90b4503

drivers/gpu/drm/i915/gvt/handlers.c

+15 −0
Original line number Diff line number Diff line
@@ -1977,6 +1977,21 @@ static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
	if (drm_WARN_ON(&i915->drm, !engine))

		return -EINVAL;



	/*

	 * Due to d3_entered is used to indicate skipping PPGTT invalidation on

	 * vGPU reset, it's set on D0->D3 on PCI config write, and cleared after

	 * vGPU reset if in resuming.

	 * In S0ix exit, the device power state also transite from D3 to D0 as

	 * S3 resume, but no vGPU reset (triggered by QEMU devic model). After

	 * S0ix exit, all engines continue to work. However the d3_entered

	 * remains set which will break next vGPU reset logic (miss the expected

	 * PPGTT invalidation).

	 * Engines can only work in D0. Thus the 1st elsp write gives GVT a

	 * chance to clear d3_entered.

	 */

	if (vgpu->d3_entered)

		vgpu->d3_entered = false;



	execlist = &vgpu->submission.execlist[engine->id];



	execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;