Commit 44ce0cd3 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
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drm/amd/display: move dispclk vco freq to clk mgr base 



This value will be needed by dml and therefore should be externally
accessible.

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarNevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e2e316d5

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

+7 −7
Original line number Diff line number Diff line
@@ -147,7 +147,7 @@ int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) 


	/* Calculate the current DFS clock, in kHz.*/

	dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR

		* clk_mgr->dentist_vco_freq_khz) / target_div;

		* clk_mgr->base.dentist_vco_freq_khz) / target_div;



	return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);

}
@@ -239,7 +239,7 @@ int dce_set_clock( 
	/* Make sure requested clock isn't lower than minimum threshold*/

	if (requested_clk_khz > 0)

		requested_clk_khz = max(requested_clk_khz,

				clk_mgr_dce->dentist_vco_freq_khz / 64);

				clk_mgr_dce->base.dentist_vco_freq_khz / 64);



	/* Prepare to program display clock*/

	pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
@@ -276,11 +276,11 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce) 
	int i;



	if (bp->integrated_info)

		clk_mgr_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;

	if (clk_mgr_dce->dentist_vco_freq_khz == 0) {

		clk_mgr_dce->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;

		if (clk_mgr_dce->dentist_vco_freq_khz == 0)

			clk_mgr_dce->dentist_vco_freq_khz = 3600000;

		clk_mgr_dce->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;

	if (clk_mgr_dce->base.dentist_vco_freq_khz == 0) {

		clk_mgr_dce->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;

		if (clk_mgr_dce->base.dentist_vco_freq_khz == 0)

			clk_mgr_dce->base.dentist_vco_freq_khz = 3600000;

	}



	/*update the maximum display clock for each power state*/

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

+2 −2
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) 
	/* Make sure requested clock isn't lower than minimum threshold*/

	if (requested_clk_khz > 0)

		requested_clk_khz = max(requested_clk_khz,

				clk_mgr_dce->dentist_vco_freq_khz / 62);

				clk_mgr_dce->base.dentist_vco_freq_khz / 62);



	dce_clk_params.target_clock_frequency = requested_clk_khz;

	dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
@@ -135,7 +135,7 @@ int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz) 
	/* Make sure requested clock isn't lower than minimum threshold*/

	if (requested_clk_khz > 0)

		requested_clk_khz = max(requested_clk_khz,

				clk_mgr->dentist_vco_freq_khz / 62);

				clk_mgr->base.dentist_vco_freq_khz / 62);



	dce_clk_params.target_clock_frequency = requested_clk_khz;

	dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

+5 −5
Original line number Diff line number Diff line
@@ -269,11 +269,11 @@ void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_ 
	clk_mgr->base.dprefclk_khz = 600000;



	if (bp->integrated_info)

		clk_mgr->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;

	if (bp->fw_info_valid && clk_mgr->dentist_vco_freq_khz == 0) {

		clk_mgr->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;

		if (clk_mgr->dentist_vco_freq_khz == 0)

			clk_mgr->dentist_vco_freq_khz = 3600000;

		clk_mgr->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;

	if (bp->fw_info_valid && clk_mgr->base.dentist_vco_freq_khz == 0) {

		clk_mgr->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;

		if (clk_mgr->base.dentist_vco_freq_khz == 0)

			clk_mgr->base.dentist_vco_freq_khz = 3600000;

	}



	if (!debug->disable_dfs_bypass && bp->integrated_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

+7 −7
Original line number Diff line number Diff line
@@ -121,9 +121,9 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, 
void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)

{

	int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR

			* clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;

			* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;

	int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR

			* clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;

			* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;



	uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);

	uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
@@ -412,7 +412,7 @@ void dcn20_clk_mgr_construct( 


	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {

		dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;

		clk_mgr->dentist_vco_freq_khz = 3850000;

		clk_mgr->base.dentist_vco_freq_khz = 3850000;



	} else {

		/* DFS Slice 2 should be used for DPREFCLK */
@@ -436,15 +436,15 @@ void dcn20_clk_mgr_construct( 
		pll_req = dc_fixpt_mul_int(pll_req, 100000);



		/* integer part is now VCO frequency in kHz */

		clk_mgr->dentist_vco_freq_khz = dc_fixpt_floor(pll_req);

		clk_mgr->base.dentist_vco_freq_khz = dc_fixpt_floor(pll_req);



		/* in case we don't get a value from the register, use default */

		if (clk_mgr->dentist_vco_freq_khz == 0)

			clk_mgr->dentist_vco_freq_khz = 3850000;

		if (clk_mgr->base.dentist_vco_freq_khz == 0)

			clk_mgr->base.dentist_vco_freq_khz = 3850000;



		/* Calculate the DPREFCLK in kHz.*/

		clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR

			* clk_mgr->dentist_vco_freq_khz) / target_div;

			* clk_mgr->base.dentist_vco_freq_khz) / target_div;

	}

	//Integrated_info table does not exist on dGPU projects so should not be referenced

	//anywhere in code for dGPUs.

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

+6 −6
Original line number Diff line number Diff line
@@ -472,7 +472,7 @@ struct clk_bw_params rn_bw_params = { 
	}

};



void rn_build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)

static void rn_build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)

{

	int i, num_valid_sets;
@@ -542,7 +542,7 @@ static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsi 
	return 0;

}



void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)

static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)

{

	int i, j = 0;
@@ -628,17 +628,17 @@ void rn_clk_mgr_construct( 


	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {

		dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;

		clk_mgr->dentist_vco_freq_khz = 3600000;

		clk_mgr->base.dentist_vco_freq_khz = 3600000;

		clk_mgr->base.dprefclk_khz = 600000;

	} else {

		struct clk_log_info log_info = {0};



		/* TODO: Check we get what we expect during bringup */

		clk_mgr->dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);

		clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);



		/* in case we don't get a value from the register, use default */

		if (clk_mgr->dentist_vco_freq_khz == 0)

			clk_mgr->dentist_vco_freq_khz = 3600000;

		if (clk_mgr->base.dentist_vco_freq_khz == 0)

			clk_mgr->base.dentist_vco_freq_khz = 3600000;



		rn_dump_clk_registers(&s, &clk_mgr->base, &log_info);

		/* Convert dprefclk units from MHz to KHz */