Commit 44aaa015 authored by Sean Christopherson's avatar Sean Christopherson Committed by Paolo Bonzini
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KVM: x86/mmu: Disable MMIO caching if MMIO value collides with L1TF 



Disable MMIO caching if the MMIO value collides with the L1TF mitigation
that usurps high PFN bits.  In practice this should never happen as only
CPUs with SME support can generate such a collision (because the MMIO
value can theoretically get adjusted into legal memory), and no CPUs
exist that support SME and are susceptible to L1TF.  But, closing the
hole is trivial.

Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
Message-Id: <20210225204749.1512652-5-seanjc@google.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent ec89e643

arch/x86/kvm/mmu/spte.c

+12 −1
Original line number Diff line number Diff line
@@ -245,8 +245,19 @@ u64 mark_spte_for_access_track(u64 spte) 
void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 access_mask)

{

	BUG_ON((u64)(unsigned)access_mask != access_mask);

	WARN_ON(mmio_value & (shadow_nonpresent_or_rsvd_mask << SHADOW_NONPRESENT_OR_RSVD_MASK_LEN));

	WARN_ON(mmio_value & shadow_nonpresent_or_rsvd_lower_gfn_mask);



	/*

	 * Disable MMIO caching if the MMIO value collides with the bits that

	 * are used to hold the relocated GFN when the L1TF mitigation is

	 * enabled.  This should never fire as there is no known hardware that

	 * can trigger this condition, e.g. SME/SEV CPUs that require a custom

	 * MMIO value are not susceptible to L1TF.

	 */

	if (WARN_ON(mmio_value & (shadow_nonpresent_or_rsvd_mask <<

				  SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)))

		mmio_value = 0;



	shadow_mmio_value = mmio_value | SPTE_MMIO_MASK;

	shadow_mmio_access_mask = access_mask;

}