Loading arch/arm/include/asm/perf_event.h +0 −4 Original line number Diff line number Diff line Loading @@ -12,10 +12,6 @@ #ifndef __ARM_PERF_EVENT_H__ #define __ARM_PERF_EVENT_H__ /* ARM performance counters start from 1 (in the cp15 accesses) so use the * same indexes here for consistency. */ #define PERF_EVENT_INDEX_OFFSET 1 /* ARM perf PMU IDs for use by internal perf clients. */ enum arm_perf_pmu_ids { ARM_PERF_PMU_ID_XSCALE1 = 0, Loading arch/frv/include/asm/perf_event.h +0 −2 Original line number Diff line number Diff line Loading @@ -12,6 +12,4 @@ #ifndef _ASM_PERF_EVENT_H #define _ASM_PERF_EVENT_H #define PERF_EVENT_INDEX_OFFSET 0 #endif /* _ASM_PERF_EVENT_H */ arch/hexagon/include/asm/perf_event.h +0 −2 Original line number Diff line number Diff line Loading @@ -19,6 +19,4 @@ #ifndef _ASM_PERF_EVENT_H #define _ASM_PERF_EVENT_H #define PERF_EVENT_INDEX_OFFSET 0 #endif /* _ASM_PERF_EVENT_H */ arch/powerpc/include/asm/perf_event_server.h +0 −2 Original line number Diff line number Diff line Loading @@ -61,8 +61,6 @@ struct pt_regs; extern unsigned long perf_misc_flags(struct pt_regs *regs); extern unsigned long perf_instruction_pointer(struct pt_regs *regs); #define PERF_EVENT_INDEX_OFFSET 1 /* * Only override the default definitions in include/linux/perf_event.h * if we have hardware PMU support. Loading arch/powerpc/kernel/perf_event.c +6 −0 Original line number Diff line number Diff line Loading @@ -1187,6 +1187,11 @@ static int power_pmu_event_init(struct perf_event *event) return err; } static int power_pmu_event_idx(struct perf_event *event) { return event->hw.idx; } struct pmu power_pmu = { .pmu_enable = power_pmu_enable, .pmu_disable = power_pmu_disable, Loading @@ -1199,6 +1204,7 @@ struct pmu power_pmu = { .start_txn = power_pmu_start_txn, .cancel_txn = power_pmu_cancel_txn, .commit_txn = power_pmu_commit_txn, .event_idx = power_pmu_event_idx, }; /* Loading Loading
arch/arm/include/asm/perf_event.h +0 −4 Original line number Diff line number Diff line Loading @@ -12,10 +12,6 @@ #ifndef __ARM_PERF_EVENT_H__ #define __ARM_PERF_EVENT_H__ /* ARM performance counters start from 1 (in the cp15 accesses) so use the * same indexes here for consistency. */ #define PERF_EVENT_INDEX_OFFSET 1 /* ARM perf PMU IDs for use by internal perf clients. */ enum arm_perf_pmu_ids { ARM_PERF_PMU_ID_XSCALE1 = 0, Loading
arch/frv/include/asm/perf_event.h +0 −2 Original line number Diff line number Diff line Loading @@ -12,6 +12,4 @@ #ifndef _ASM_PERF_EVENT_H #define _ASM_PERF_EVENT_H #define PERF_EVENT_INDEX_OFFSET 0 #endif /* _ASM_PERF_EVENT_H */
arch/hexagon/include/asm/perf_event.h +0 −2 Original line number Diff line number Diff line Loading @@ -19,6 +19,4 @@ #ifndef _ASM_PERF_EVENT_H #define _ASM_PERF_EVENT_H #define PERF_EVENT_INDEX_OFFSET 0 #endif /* _ASM_PERF_EVENT_H */
arch/powerpc/include/asm/perf_event_server.h +0 −2 Original line number Diff line number Diff line Loading @@ -61,8 +61,6 @@ struct pt_regs; extern unsigned long perf_misc_flags(struct pt_regs *regs); extern unsigned long perf_instruction_pointer(struct pt_regs *regs); #define PERF_EVENT_INDEX_OFFSET 1 /* * Only override the default definitions in include/linux/perf_event.h * if we have hardware PMU support. Loading
arch/powerpc/kernel/perf_event.c +6 −0 Original line number Diff line number Diff line Loading @@ -1187,6 +1187,11 @@ static int power_pmu_event_init(struct perf_event *event) return err; } static int power_pmu_event_idx(struct perf_event *event) { return event->hw.idx; } struct pmu power_pmu = { .pmu_enable = power_pmu_enable, .pmu_disable = power_pmu_disable, Loading @@ -1199,6 +1204,7 @@ struct pmu power_pmu = { .start_txn = power_pmu_start_txn, .cancel_txn = power_pmu_cancel_txn, .commit_txn = power_pmu_commit_txn, .event_idx = power_pmu_event_idx, }; /* Loading