Commit 44a4b9ad authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Update westmereex event topics 

Apply topic updates from:

https://github.com/intel/event-converter-for-linux-perf/



Signed-off-by: default avatarIan Rogers <irogers@google.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220413210503.3256922-11-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 7f2c72fa

tools/perf/pmu-events/arch/x86/westmereex/other.json

+1 −65
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Early Branch Prediciton Unit clears",

        "Counter": "0,1,2,3",

        "EventCode": "0xE8",

        "EventName": "BPU_CLEARS.EARLY",

        "SampleAfterValue": "2000000",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Late Branch Prediction Unit clears",

        "Counter": "0,1,2,3",

        "EventCode": "0xE8",

        "EventName": "BPU_CLEARS.LATE",

        "SampleAfterValue": "2000000",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Branch prediction unit missed call or return",

        "Counter": "0,1,2,3",

        "EventCode": "0xE5",

        "EventName": "BPU_MISSED_CALL_RET",

        "SampleAfterValue": "2000000",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "ES segment renames",

        "Counter": "0,1,2,3",
@@ -127,46 +103,6 @@ 
        "SampleAfterValue": "200000",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "All RAT stall cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0xD2",

        "EventName": "RAT_STALLS.ANY",

        "SampleAfterValue": "2000000",

        "UMask": "0xf"

    },

    {

        "BriefDescription": "Flag stall cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0xD2",

        "EventName": "RAT_STALLS.FLAGS",

        "SampleAfterValue": "2000000",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Partial register stall cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0xD2",

        "EventName": "RAT_STALLS.REGISTERS",

        "SampleAfterValue": "2000000",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "ROB read port stalls cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0xD2",

        "EventName": "RAT_STALLS.ROB_READ_PORT",

        "SampleAfterValue": "2000000",

        "UMask": "0x4"

    },

    {

        "BriefDescription": "Scoreboard stall cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0xD2",

        "EventName": "RAT_STALLS.SCOREBOARD",

        "SampleAfterValue": "2000000",

        "UMask": "0x8"

    },

    {

        "BriefDescription": "All Store buffer stall cycles",

        "Counter": "0,1,2,3",

tools/perf/pmu-events/arch/x86/westmereex/pipeline.json

+65 −1
Original line number Diff line number Diff line
@@ -50,6 +50,30 @@ 
        "SampleAfterValue": "2000000",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Early Branch Prediciton Unit clears",

        "Counter": "0,1,2,3",

        "EventCode": "0xE8",

        "EventName": "BPU_CLEARS.EARLY",

        "SampleAfterValue": "2000000",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Late Branch Prediction Unit clears",

        "Counter": "0,1,2,3",

        "EventCode": "0xE8",

        "EventName": "BPU_CLEARS.LATE",

        "SampleAfterValue": "2000000",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Branch prediction unit missed call or return",

        "Counter": "0,1,2,3",

        "EventCode": "0xE5",

        "EventName": "BPU_MISSED_CALL_RET",

        "SampleAfterValue": "2000000",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Branch instructions decoded",

        "Counter": "0,1,2,3",
@@ -494,6 +518,46 @@ 
        "SampleAfterValue": "20000",

        "UMask": "0x4"

    },

    {

        "BriefDescription": "All RAT stall cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0xD2",

        "EventName": "RAT_STALLS.ANY",

        "SampleAfterValue": "2000000",

        "UMask": "0xf"

    },

    {

        "BriefDescription": "Flag stall cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0xD2",

        "EventName": "RAT_STALLS.FLAGS",

        "SampleAfterValue": "2000000",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Partial register stall cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0xD2",

        "EventName": "RAT_STALLS.REGISTERS",

        "SampleAfterValue": "2000000",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "ROB read port stalls cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0xD2",

        "EventName": "RAT_STALLS.ROB_READ_PORT",

        "SampleAfterValue": "2000000",

        "UMask": "0x4"

    },

    {

        "BriefDescription": "Scoreboard stall cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0xD2",

        "EventName": "RAT_STALLS.SCOREBOARD",

        "SampleAfterValue": "2000000",

        "UMask": "0x8"

    },

    {

        "BriefDescription": "Resource related stall cycles",

        "Counter": "0,1,2,3",