Commit 449c695d authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Stephen Boyd
Browse files

clk: tegra124: Remove lock-enable bit from PLLM 



According to the Tegra124 TRM documentation, PLLM_MISC2 register doesn't
have the lock-enable bit as well as any other PLLM-related register. Hence
PLLM re-locking can't be initiated by software. The incorrect bit setting
should have been harmless since that bit is undefined according to TRM.

Tested-by: default avatarSteev Klimaszewski <steev@kali.org>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Acked-By: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 40db569d

drivers/clk/tegra/clk-tegra124.c

+1 −2
Original line number Diff line number Diff line
@@ -413,7 +413,6 @@ static struct tegra_clk_pll_params pll_m_params = { 
	.base_reg = PLLM_BASE,

	.misc_reg = PLLM_MISC,

	.lock_mask = PLL_BASE_LOCK,

	.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,

	.lock_delay = 300,

	.max_p = 5,

	.pdiv_tohw = pllm_p,
@@ -421,7 +420,7 @@ static struct tegra_clk_pll_params pll_m_params = { 
	.pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,

	.pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,

	.freq_table = pll_m_freq_table,

	.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,

	.flags = TEGRA_PLL_USE_LOCK,

};



static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {