Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net (446bf64b) · Commits · EulixOS / Software / Kernel

Documentation/admin-guide/sysctl/net.rst

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		@@ -39,7 +39,6 @@ Table : Subdirectories in /proc/sys/net
		802 E802 protocol ax25 AX25
		ethernet Ethernet protocol rose X.25 PLP layer
		ipv4 IP version 4 x25 X.25 protocol
		ipx IPX token-ring IBM token ring
		bridge Bridging decnet DEC net
		ipv6 IP version 6 tipc TIPC
		========= =================== = ========== ==================
		@@ -401,33 +400,7 @@ interface.
		(network) that the route leads to, the router (may be directly connected), the
		route flags, and the device the route is using.


		5. IPX
		------

		The IPX protocol has no tunable values in proc/sys/net.

		The IPX protocol does, however, provide proc/net/ipx. This lists each IPX
		socket giving the local and remote addresses in Novell format (that is
		network:node:port). In accordance with the strange Novell tradition,
		everything but the port is in hex. Not_Connected is displayed for sockets that
		are not tied to a specific remote address. The Tx and Rx queue sizes indicate
		the number of bytes pending for transmission and reception. The state
		indicates the state the socket is in and the uid is the owning uid of the
		socket.

		The /proc/net/ipx_interface file lists all IPX interfaces. For each interface
		it gives the network number, the node number, and indicates if the network is
		the primary network. It also indicates which device it is bound to (or
		Internal for internal networks) and the Frame Type if appropriate. Linux
		supports 802.3, 802.2, 802.2 SNAP and DIX (Blue Book) ethernet framing for
		IPX.

		The /proc/net/ipx_route table holds a list of IPX routes. For each route it
		gives the destination network, the router node (or Directly) and the network
		address of the router (or Connected) for internal networks.

		6. TIPC
		5. TIPC
		-------

		tipc_rmem

Documentation/devicetree/bindings/Makefile

+3 −1

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		@@ -19,7 +19,9 @@ quiet_cmd_mk_schema = SCHEMA $@

		DT_DOCS = $(shell \
		cd $(srctree)/$(src) && \
		find * $ -name '*.yaml' ! -name $(DT_TMP_SCHEMA) $ \
		find * \( -name '*.yaml' ! \
		-name $(DT_TMP_SCHEMA) ! \
		-name '*.example.dt.yaml' \) \
		)

		DT_SCHEMA_FILES ?= $(addprefix $(src)/,$(DT_DOCS))

Documentation/devicetree/bindings/net/fsl-fec.txt

+17 −13

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		@@ -7,18 +7,6 @@ Required properties:
		- phy-mode : See ethernet.txt file in the same directory

		Optional properties:
		- phy-reset-gpios : Should specify the gpio for phy reset
		- phy-reset-duration : Reset duration in milliseconds. Should present
		only if property "phy-reset-gpios" is available. Missing the property
		will have the duration be 1 millisecond. Numbers greater than 1000 are
		invalid and 1 millisecond will be used instead.
		- phy-reset-active-high : If present then the reset sequence using the GPIO
		specified in the "phy-reset-gpios" property is reversed (H=reset state,
		L=operation state).
		- phy-reset-post-delay : Post reset delay in milliseconds. If present then
		a delay of phy-reset-post-delay milliseconds will be observed after the
		phy-reset-gpios has been toggled. Can be omitted thus no delay is
		observed. Delay is in range of 1ms to 1000ms. Other delays are invalid.
		- phy-supply : regulator that powers the Ethernet PHY.
		- phy-handle : phandle to the PHY device connected to this device.
		- fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
		@@ -47,11 +35,27 @@ Optional properties:
		For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse
		per second interrupt associated with 1588 precision time protocol(PTP).


		Optional subnodes:
		- mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
		according to phy.txt in the same directory

		Deprecated optional properties:
		To avoid these, create a phy node according to phy.txt in the same
		directory, and point the fec's "phy-handle" property to it. Then use
		the phy's reset binding, again described by phy.txt.
		- phy-reset-gpios : Should specify the gpio for phy reset
		- phy-reset-duration : Reset duration in milliseconds. Should present
		only if property "phy-reset-gpios" is available. Missing the property
		will have the duration be 1 millisecond. Numbers greater than 1000 are
		invalid and 1 millisecond will be used instead.
		- phy-reset-active-high : If present then the reset sequence using the GPIO
		specified in the "phy-reset-gpios" property is reversed (H=reset state,
		L=operation state).
		- phy-reset-post-delay : Post reset delay in milliseconds. If present then
		a delay of phy-reset-post-delay milliseconds will be observed after the
		phy-reset-gpios has been toggled. Can be omitted thus no delay is
		observed. Delay is in range of 1ms to 1000ms. Other delays are invalid.

		Example:

		ethernet@83fec000 {

Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml

+2 −1

Original line number	Diff line number	Diff line
		@@ -37,7 +37,8 @@ properties:
		hwlocks: true

		st,syscfg:
		$ref: "/schemas/types.yaml#/definitions/phandle-array"
		allOf:
		- $ref: "/schemas/types.yaml#/definitions/phandle-array"
		description: Should be phandle/offset/mask
		items:
		- description: Phandle to the syscon node which includes IRQ mux selection.

Documentation/devicetree/bindings/riscv/cpus.txt

deleted100644 → 0

+0 −162

Original line number	Diff line number	Diff line
		===================
		RISC-V CPU Bindings
		===================

		The device tree allows to describe the layout of CPUs in a system through
		the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
		defining properties for every cpu.

		Bindings for CPU nodes follow the Devicetree Specification, available from:

		https://www.devicetree.org/specifications/

		with updates for 32-bit and 64-bit RISC-V systems provided in this document.

		===========
		Terminology
		===========

		This document uses some terminology common to the RISC-V community that is not
		widely used, the definitions of which are listed here:

		* hart: A hardware execution context, which contains all the state mandated by
		the RISC-V ISA: a PC and some registers. This terminology is designed to
		disambiguate software's view of execution contexts from any particular
		microarchitectural implementation strategy. For example, my Intel laptop is
		described as having one socket with two cores, each of which has two hyper
		threads. Therefore this system has four harts.

		=====================================
		cpus and cpu node bindings definition
		=====================================

		The RISC-V architecture, in accordance with the Devicetree Specification,
		requires the cpus and cpu nodes to be present and contain the properties
		described below.

		- cpus node

		Description: Container of cpu nodes

		The node name must be "cpus".

		A cpus node must define the following properties:

		- #address-cells
		Usage: required
		Value type: <u32>
		Definition: must be set to 1
		- #size-cells
		Usage: required
		Value type: <u32>
		Definition: must be set to 0

		- cpu node

		Description: Describes a hart context

		PROPERTIES

		- device_type
		Usage: required
		Value type: <string>
		Definition: must be "cpu"
		- reg
		Usage: required
		Value type: <u32>
		Definition: The hart ID of this CPU node
		- compatible:
		Usage: required
		Value type: <stringlist>
		Definition: must contain "riscv", may contain one of
		"sifive,rocket0"
		- mmu-type:
		Usage: optional
		Value type: <string>
		Definition: Specifies the CPU's MMU type. Possible values are
		"riscv,sv32"
		"riscv,sv39"
		"riscv,sv48"
		- riscv,isa:
		Usage: required
		Value type: <string>
		Definition: Contains the RISC-V ISA string of this hart. These
		ISA strings are defined by the RISC-V ISA manual.

		Example: SiFive Freedom U540G Development Kit
		---------------------------------------------

		This system contains two harts: a hart marked as disabled that's used for
		low-level system tasks and should be ignored by Linux, and a second hart that
		Linux is allowed to run on.

		cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <1000000>;
		cpu@0 {
		clock-frequency = <1600000000>;
		compatible = "sifive,rocket0", "riscv";
		device_type = "cpu";
		i-cache-block-size = <64>;
		i-cache-sets = <128>;
		i-cache-size = <16384>;
		next-level-cache = <&L15 &L0>;
		reg = <0>;
		riscv,isa = "rv64imac";
		status = "disabled";
		L10: interrupt-controller {
		#interrupt-cells = <1>;
		compatible = "riscv,cpu-intc";
		interrupt-controller;
		};
		};
		cpu@1 {
		clock-frequency = <1600000000>;
		compatible = "sifive,rocket0", "riscv";
		d-cache-block-size = <64>;
		d-cache-sets = <64>;
		d-cache-size = <32768>;
		d-tlb-sets = <1>;
		d-tlb-size = <32>;
		device_type = "cpu";
		i-cache-block-size = <64>;
		i-cache-sets = <64>;
		i-cache-size = <32768>;
		i-tlb-sets = <1>;
		i-tlb-size = <32>;
		mmu-type = "riscv,sv39";
		next-level-cache = <&L15 &L0>;
		reg = <1>;
		riscv,isa = "rv64imafdc";
		status = "okay";
		tlb-split;
		L13: interrupt-controller {
		#interrupt-cells = <1>;
		compatible = "riscv,cpu-intc";
		interrupt-controller;
		};
		};
		};

		Example: Spike ISA Simulator with 1 Hart
		----------------------------------------

		This device tree matches the Spike ISA golden model as run with `spike -p1`.

		cpus {
		cpu@0 {
		device_type = "cpu";
		reg = <0x00000000>;
		status = "okay";
		compatible = "riscv";
		riscv,isa = "rv64imafdc";
		mmu-type = "riscv,sv48";
		clock-frequency = <0x3b9aca00>;
		interrupt-controller {
		#interrupt-cells = <0x00000001>;
		interrupt-controller;
		compatible = "riscv,cpu-intc";
		}
		}
		}