clk: qcom: videocc-sm8450: Add video clock controller driver for SM8450 (441fe711) · Commits · EulixOS / Software / Kernel

drivers/clk/qcom/Kconfig

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		@@ -971,4 +971,13 @@ config CLK_GFM_LPASS_SM8250
		Support for the Glitch Free Mux (GFM) Low power audio
		subsystem (LPASS) clocks found on SM8250 SoCs.

		config SM_VIDEOCC_8450
		tristate "SM8450 Video Clock Controller"
		select SM_GCC_8450
		select QCOM_GDSC
		help
		Support for the video clock controller on Qualcomm Technologies, Inc.
		SM8450 devices.
		Say Y if you want to support video devices and functionality such as
		video encode/decode.
		endif

drivers/clk/qcom/Makefile

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		@@ -128,6 +128,7 @@ obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
		obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
		obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
		obj-$(CONFIG_SM_VIDEOCC_8350) += videocc-sm8350.o
		obj-$(CONFIG_SM_VIDEOCC_8450) += videocc-sm8450.o
		obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
		obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
		obj-$(CONFIG_QCOM_HFPLL) += hfpll.o

drivers/clk/qcom/videocc-sm8450.c

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		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
		*/

		#include <linux/clk-provider.h>
		#include <linux/module.h>
		#include <linux/of_device.h>
		#include <linux/pm_runtime.h>
		#include <linux/regmap.h>

		#include <dt-bindings/clock/qcom,sm8450-videocc.h>

		#include "clk-alpha-pll.h"
		#include "clk-branch.h"
		#include "clk-rcg.h"
		#include "clk-regmap.h"
		#include "clk-regmap-divider.h"
		#include "common.h"
		#include "gdsc.h"
		#include "reset.h"

		enum {
		DT_BI_TCXO,
		};

		enum {
		P_BI_TCXO,
		P_VIDEO_CC_PLL0_OUT_MAIN,
		P_VIDEO_CC_PLL1_OUT_MAIN,
		};

		static const struct pll_vco lucid_evo_vco[] = {
		{ 249600000, 2020000000, 0 },
		};

		static const struct alpha_pll_config video_cc_pll0_config = {
		/* .l includes CAL_L_VAL, L_VAL fields */
		.l = 0x0044001e,
		.alpha = 0x0,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00182261,
		.config_ctl_hi1_val = 0x32aa299c,
		.user_ctl_val = 0x00000000,
		.user_ctl_hi_val = 0x00000805,
		};

		static struct clk_alpha_pll video_cc_pll0 = {
		.offset = 0x0,
		.vco_table = lucid_evo_vco,
		.num_vco = ARRAY_SIZE(lucid_evo_vco),
		.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
		.clkr = {
		.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_pll0",
		.parent_data = &(const struct clk_parent_data) {
		.index = DT_BI_TCXO,
		},
		.num_parents = 1,
		.ops = &clk_alpha_pll_lucid_evo_ops,
		},
		},
		};

		static const struct alpha_pll_config video_cc_pll1_config = {
		/* .l includes CAL_L_VAL, L_VAL fields */
		.l = 0x0044002b,
		.alpha = 0xc000,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00182261,
		.config_ctl_hi1_val = 0x32aa299c,
		.user_ctl_val = 0x00000000,
		.user_ctl_hi_val = 0x00000805,
		};

		static struct clk_alpha_pll video_cc_pll1 = {
		.offset = 0x1000,
		.vco_table = lucid_evo_vco,
		.num_vco = ARRAY_SIZE(lucid_evo_vco),
		.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
		.clkr = {
		.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_pll1",
		.parent_data = &(const struct clk_parent_data) {
		.index = DT_BI_TCXO,
		},
		.num_parents = 1,
		.ops = &clk_alpha_pll_lucid_evo_ops,
		},
		},
		};

		static const struct parent_map video_cc_parent_map_0[] = {
		{ P_BI_TCXO, 0 },
		{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
		};

		static const struct clk_parent_data video_cc_parent_data_0[] = {
		{ .index = DT_BI_TCXO },
		{ .hw = &video_cc_pll0.clkr.hw },
		};

		static const struct parent_map video_cc_parent_map_1[] = {
		{ P_BI_TCXO, 0 },
		{ P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
		};

		static const struct clk_parent_data video_cc_parent_data_1[] = {
		{ .index = DT_BI_TCXO },
		{ .hw = &video_cc_pll1.clkr.hw },
		};

		static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
		F(576000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
		F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
		F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
		F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
		F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 video_cc_mvs0_clk_src = {
		.cmd_rcgr = 0x8000,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = video_cc_parent_map_0,
		.freq_tbl = ftbl_video_cc_mvs0_clk_src,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs0_clk_src",
		.parent_data = video_cc_parent_data_0,
		.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_shared_ops,
		},
		};

		static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
		F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
		F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
		F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
		F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
		F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 video_cc_mvs1_clk_src = {
		.cmd_rcgr = 0x8018,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = video_cc_parent_map_1,
		.freq_tbl = ftbl_video_cc_mvs1_clk_src,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs1_clk_src",
		.parent_data = video_cc_parent_data_1,
		.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_shared_ops,
		},
		};

		static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
		.reg = 0x80b8,
		.shift = 0,
		.width = 4,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs0_div_clk_src",
		.parent_hws = (const struct clk_hw*[]) {
		&video_cc_mvs0_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_regmap_div_ro_ops,
		},
		};

		static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
		.reg = 0x806c,
		.shift = 0,
		.width = 4,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs0c_div2_div_clk_src",
		.parent_hws = (const struct clk_hw*[]) {
		&video_cc_mvs0_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_regmap_div_ro_ops,
		},
		};

		static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
		.reg = 0x80dc,
		.shift = 0,
		.width = 4,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs1_div_clk_src",
		.parent_hws = (const struct clk_hw*[]) {
		&video_cc_mvs1_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_regmap_div_ro_ops,
		},
		};

		static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
		.reg = 0x8094,
		.shift = 0,
		.width = 4,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs1c_div2_div_clk_src",
		.parent_hws = (const struct clk_hw*[]) {
		&video_cc_mvs1_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_regmap_div_ro_ops,
		},
		};

		static struct clk_branch video_cc_mvs0_clk = {
		.halt_reg = 0x80b0,
		.halt_check = BRANCH_HALT_SKIP,
		.hwcg_reg = 0x80b0,
		.hwcg_bit = 1,
		.clkr = {
		.enable_reg = 0x80b0,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs0_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&video_cc_mvs0_div_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvs0c_clk = {
		.halt_reg = 0x8064,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x8064,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs0c_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvs1_clk = {
		.halt_reg = 0x80d4,
		.halt_check = BRANCH_HALT_SKIP,
		.hwcg_reg = 0x80d4,
		.hwcg_bit = 1,
		.clkr = {
		.enable_reg = 0x80d4,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs1_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&video_cc_mvs1_div_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvs1c_clk = {
		.halt_reg = 0x808c,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x808c,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs1c_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct gdsc video_cc_mvs0c_gdsc = {
		.gdscr = 0x804c,
		.en_rest_wait_val = 0x2,
		.en_few_wait_val = 0x2,
		.clk_dis_wait_val = 0x6,
		.pd = {
		.name = "video_cc_mvs0c_gdsc",
		},
		.pwrsts = PWRSTS_OFF_ON,
		.flags = RETAIN_FF_ENABLE,
		};

		static struct gdsc video_cc_mvs0_gdsc = {
		.gdscr = 0x809c,
		.en_rest_wait_val = 0x2,
		.en_few_wait_val = 0x2,
		.clk_dis_wait_val = 0x6,
		.pd = {
		.name = "video_cc_mvs0_gdsc",
		},
		.pwrsts = PWRSTS_OFF_ON,
		.parent = &video_cc_mvs0c_gdsc.pd,
		.flags = RETAIN_FF_ENABLE \| HW_CTRL,
		};

		static struct gdsc video_cc_mvs1c_gdsc = {
		.gdscr = 0x8074,
		.en_rest_wait_val = 0x2,
		.en_few_wait_val = 0x2,
		.clk_dis_wait_val = 0x6,
		.pd = {
		.name = "video_cc_mvs1c_gdsc",
		},
		.pwrsts = PWRSTS_OFF_ON,
		.flags = RETAIN_FF_ENABLE,
		};

		static struct gdsc video_cc_mvs1_gdsc = {
		.gdscr = 0x80c0,
		.en_rest_wait_val = 0x2,
		.en_few_wait_val = 0x2,
		.clk_dis_wait_val = 0x6,
		.pd = {
		.name = "video_cc_mvs1_gdsc",
		},
		.pwrsts = PWRSTS_OFF_ON,
		.parent = &video_cc_mvs1c_gdsc.pd,
		.flags = RETAIN_FF_ENABLE \| HW_CTRL,
		};

		static struct clk_regmap *video_cc_sm8450_clocks[] = {
		[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
		[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
		[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
		[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
		[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
		[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
		[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
		[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
		[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
		[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
		[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
		[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
		};

		static struct gdsc *video_cc_sm8450_gdscs[] = {
		[VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
		[VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
		[VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc,
		[VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc,
		};

		static const struct qcom_reset_map video_cc_sm8450_resets[] = {
		[CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80e0 },
		[CVP_VIDEO_CC_MVS0_BCR] = { 0x8098 },
		[CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
		[CVP_VIDEO_CC_MVS1_BCR] = { 0x80bc },
		[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8070 },
		[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
		[VIDEO_CC_MVS1C_CLK_ARES] = { 0x808c, 2 },
		};

		static const struct regmap_config video_cc_sm8450_regmap_config = {
		.reg_bits = 32,
		.reg_stride = 4,
		.val_bits = 32,
		.max_register = 0x9f4c,
		.fast_io = true,
		};

		static struct qcom_cc_desc video_cc_sm8450_desc = {
		.config = &video_cc_sm8450_regmap_config,
		.clks = video_cc_sm8450_clocks,
		.num_clks = ARRAY_SIZE(video_cc_sm8450_clocks),
		.resets = video_cc_sm8450_resets,
		.num_resets = ARRAY_SIZE(video_cc_sm8450_resets),
		.gdscs = video_cc_sm8450_gdscs,
		.num_gdscs = ARRAY_SIZE(video_cc_sm8450_gdscs),
		};

		static const struct of_device_id video_cc_sm8450_match_table[] = {
		{ .compatible = "qcom,sm8450-videocc" },
		{ }
		};
		MODULE_DEVICE_TABLE(of, video_cc_sm8450_match_table);

		static int video_cc_sm8450_probe(struct platform_device *pdev)
		{
		struct regmap *regmap;
		int ret;

		ret = devm_pm_runtime_enable(&pdev->dev);
		if (ret)
		return ret;

		ret = pm_runtime_resume_and_get(&pdev->dev);
		if (ret)
		return ret;

		regmap = qcom_cc_map(pdev, &video_cc_sm8450_desc);
		if (IS_ERR(regmap)) {
		pm_runtime_put(&pdev->dev);
		return PTR_ERR(regmap);
		}

		clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
		clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);

		/*
		* Keep clocks always enabled:
		* video_cc_ahb_clk
		* video_cc_sleep_clk
		* video_cc_xo_clk
		*/
		regmap_update_bits(regmap, 0x80e4, BIT(0), BIT(0));
		regmap_update_bits(regmap, 0x8130, BIT(0), BIT(0));
		regmap_update_bits(regmap, 0x8114, BIT(0), BIT(0));

		ret = qcom_cc_really_probe(pdev, &video_cc_sm8450_desc, regmap);

		pm_runtime_put(&pdev->dev);

		return ret;
		}

		static struct platform_driver video_cc_sm8450_driver = {
		.probe = video_cc_sm8450_probe,
		.driver = {
		.name = "video_cc-sm8450",
		.of_match_table = video_cc_sm8450_match_table,
		},
		};

		static int __init video_cc_sm8450_init(void)
		{
		return platform_driver_register(&video_cc_sm8450_driver);
		}
		subsys_initcall(video_cc_sm8450_init);

		static void __exit video_cc_sm8450_exit(void)
		{
		platform_driver_unregister(&video_cc_sm8450_driver);
		}
		module_exit(video_cc_sm8450_exit);

		MODULE_DESCRIPTION("QTI VIDEOCC SM8450 Driver");
		MODULE_LICENSE("GPL");