Commit 441decf9 authored by Chun-Jie Chen's avatar Chun-Jie Chen Committed by Stephen Boyd
Browse files

clk: mediatek: Add MT8192 vencsys clock support 



Add MT8192 vencsys clock provider

Signed-off-by: default avatarWeiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: default avatarChun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210726105719.15793-22-chun-jie.chen@mediatek.com


Reviewed-by: default avatarIkjoon Jang <ikjn@chromium.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 25f3d97e

drivers/clk/mediatek/Kconfig

+6 −0
Original line number Diff line number Diff line
@@ -574,6 +574,12 @@ config COMMON_CLK_MT8192_VDECSYS 
	help

	  This driver supports MediaTek MT8192 vdecsys and vdecsys_soc clocks.



config COMMON_CLK_MT8192_VENCSYS

	bool "Clock driver for MediaTek MT8192 vencsys"

	depends on COMMON_CLK_MT8192

	help

	  This driver supports MediaTek MT8192 vencsys clocks.



config COMMON_CLK_MT8516

	bool "Clock driver for MediaTek MT8516"

	depends on ARCH_MEDIATEK || COMPILE_TEST

drivers/clk/mediatek/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -79,5 +79,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MMSYS) += clk-mt8192-mm.o 
obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o

obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o

obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o

obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o

obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o

obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o

drivers/clk/mediatek/clk-mt8192-venc.c

0 → 100644
+53 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

//

// Copyright (c) 2021 MediaTek Inc.

// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>



#include <linux/clk-provider.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>



#include "clk-mtk.h"

#include "clk-gate.h"



#include <dt-bindings/clock/mt8192-clk.h>



static const struct mtk_gate_regs venc_cg_regs = {

	.set_ofs = 0x4,

	.clr_ofs = 0x8,

	.sta_ofs = 0x0,

};



#define GATE_VENC(_id, _name, _parent, _shift)	\

	GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)



static const struct mtk_gate venc_clks[] = {

	GATE_VENC(CLK_VENC_SET0_LARB, "venc_set0_larb", "venc_sel", 0),

	GATE_VENC(CLK_VENC_SET1_VENC, "venc_set1_venc", "venc_sel", 4),

	GATE_VENC(CLK_VENC_SET2_JPGENC, "venc_set2_jpgenc", "venc_sel", 8),

	GATE_VENC(CLK_VENC_SET5_GALS, "venc_set5_gals", "venc_sel", 28),

};



static const struct mtk_clk_desc venc_desc = {

	.clks = venc_clks,

	.num_clks = ARRAY_SIZE(venc_clks),

};



static const struct of_device_id of_match_clk_mt8192_venc[] = {

	{

		.compatible = "mediatek,mt8192-vencsys",

		.data = &venc_desc,

	}, {

		/* sentinel */

	}

};



static struct platform_driver clk_mt8192_venc_drv = {

	.probe = mtk_clk_simple_probe,

	.driver = {

		.name = "clk-mt8192-venc",

		.of_match_table = of_match_clk_mt8192_venc,

	},

};



builtin_platform_driver(clk_mt8192_venc_drv);