Commit 441555c6 authored by Suravee Suthikulpanit's avatar Suravee Suthikulpanit Committed by Joerg Roedel
Browse files

iommu/amd: Introduce iommu_v1_iova_to_phys 



This implements iova_to_phys for AMD IOMMU v1 pagetable,
which will be used by the IO page table framework.

Signed-off-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Link: https://lore.kernel.org/r/20201215073705.123786-12-suravee.suthikulpanit@amd.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 0633bbcc

drivers/iommu/amd/io_pgtable.c

+22 −0
Original line number Diff line number Diff line
@@ -488,6 +488,26 @@ unsigned long iommu_unmap_page(struct protection_domain *dom, 
	return unmapped;

}



static phys_addr_t iommu_v1_iova_to_phys(struct io_pgtable_ops *ops, unsigned long iova)

{

	struct amd_io_pgtable *pgtable = io_pgtable_ops_to_data(ops);

	unsigned long offset_mask, pte_pgsize;

	u64 *pte, __pte;



	if (pgtable->mode == PAGE_MODE_NONE)

		return iova;



	pte = fetch_pte(pgtable, iova, &pte_pgsize);



	if (!pte || !IOMMU_PTE_PRESENT(*pte))

		return 0;



	offset_mask = pte_pgsize - 1;

	__pte	    = __sme_clr(*pte & PM_ADDR_MASK);



	return (__pte & ~offset_mask) | (iova & offset_mask);

}



/*

 * ----------------------------------------------------

 */
@@ -528,6 +548,8 @@ static struct io_pgtable *v1_alloc_pgtable(struct io_pgtable_cfg *cfg, void *coo 
	cfg->oas            = IOMMU_OUT_ADDR_BIT_SIZE,

	cfg->tlb            = &v1_flush_ops;



	pgtable->iop.ops.iova_to_phys = iommu_v1_iova_to_phys;



	return &pgtable->iop;

}

drivers/iommu/amd/iommu.c

+1 −15
Original line number Diff line number Diff line
@@ -2100,22 +2100,8 @@ static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, 
{

	struct protection_domain *domain = to_pdomain(dom);

	struct io_pgtable_ops *ops = &domain->iop.iop.ops;

	struct amd_io_pgtable *pgtable = io_pgtable_ops_to_data(ops);

	unsigned long offset_mask, pte_pgsize;

	u64 *pte, __pte;



	if (domain->iop.mode == PAGE_MODE_NONE)

		return iova;



	pte = fetch_pte(pgtable, iova, &pte_pgsize);



	if (!pte || !IOMMU_PTE_PRESENT(*pte))

		return 0;



	offset_mask = pte_pgsize - 1;

	__pte	    = __sme_clr(*pte & PM_ADDR_MASK);



	return (__pte & ~offset_mask) | (iova & offset_mask);

	return ops->iova_to_phys(ops, iova);

}



static bool amd_iommu_capable(enum iommu_cap cap)