Commit 43f09605 authored by Xingyu Wu's avatar Xingyu Wu Committed by Conor Dooley
Browse files

riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks 



Add DVP and HDMI TX pixel external fixed clocks and the rates are
74.25MHz and 297MHz.

Acked-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: default avatarEmil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarXingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 66bd0770

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -38,6 +38,10 @@ 
	};

};



&dvp_clk {

	clock-frequency = <74250000>;

};



&gmac0_rgmii_rxin {

	clock-frequency = <125000000>;

};
@@ -54,6 +58,10 @@ 
	clock-frequency = <50000000>;

};



&hdmitx0_pixelclk {

	clock-frequency = <297000000>;

};



&i2srx_bclk_ext {

	clock-frequency = <12288000>;

};

arch/riscv/boot/dts/starfive/jh7110.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -197,6 +197,12 @@ 
			};

	};



	dvp_clk: dvp-clock {

		compatible = "fixed-clock";

		clock-output-names = "dvp_clk";

		#clock-cells = <0>;

	};



	gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {

		compatible = "fixed-clock";

		clock-output-names = "gmac0_rgmii_rxin";
@@ -221,6 +227,12 @@ 
		#clock-cells = <0>;

	};



	hdmitx0_pixelclk: hdmitx0-pixel-clock {

		compatible = "fixed-clock";

		clock-output-names = "hdmitx0_pixelclk";

		#clock-cells = <0>;

	};



	i2srx_bclk_ext: i2srx-bclk-ext-clock {

		compatible = "fixed-clock";

		clock-output-names = "i2srx_bclk_ext";