Commit 43d48bbb authored by Chunfeng Yun's avatar Chunfeng Yun Committed by Greg Kroah-Hartman
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usb: xhci-mtk: add support ip-sleep wakeup for mt8195



Add support ip-sleep wakeup for mt8195, it's a specific revision for
each USB controller, and not following IPM rule.

Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: default avatarChunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/20220128062902.26273-2-chunfeng.yun@mediatek.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 8609e3e1
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+37 −0
Original line number Diff line number Diff line
@@ -95,6 +95,19 @@
#define WC0_SSUSB0_CDEN		BIT(6)
#define WC0_IS_SPM_EN		BIT(1)

/* mt8195 */
#define PERI_WK_CTRL0_8195	0x04
#define WC0_IS_P_95		BIT(30)	/* polarity */
#define WC0_IS_C_95(x)		((u32)(((x) & 0x7) << 27))
#define WC0_IS_EN_P3_95		BIT(26)
#define WC0_IS_EN_P2_95		BIT(25)
#define WC0_IS_EN_P1_95		BIT(24)

#define PERI_WK_CTRL1_8195	0x20
#define WC1_IS_C_95(x)		((u32)(((x) & 0xf) << 28))
#define WC1_IS_P_95		BIT(12)
#define WC1_IS_EN_P0_95		BIT(6)

/* mt2712 etc */
#define PERI_SSUSB_SPM_CTRL	0x0
#define SSC_IP_SLEEP_EN	BIT(4)
@@ -105,6 +118,10 @@ enum ssusb_uwk_vers {
	SSUSB_UWK_V2,
	SSUSB_UWK_V1_1 = 101,	/* specific revision 1.01 */
	SSUSB_UWK_V1_2,		/* specific revision 1.2 */
	SSUSB_UWK_V1_3,		/* mt8195 IP0 */
	SSUSB_UWK_V1_4,		/* mt8195 IP1 */
	SSUSB_UWK_V1_5,		/* mt8195 IP2 */
	SSUSB_UWK_V1_6,		/* mt8195 IP3 */
};

/*
@@ -308,6 +325,26 @@ static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
		msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
		val = enable ? msk : 0;
		break;
	case SSUSB_UWK_V1_3:
		reg = mtk->uwk_reg_base + PERI_WK_CTRL1_8195;
		msk = WC1_IS_EN_P0_95 | WC1_IS_C_95(0xf) | WC1_IS_P_95;
		val = enable ? (WC1_IS_EN_P0_95 | WC1_IS_C_95(0x1)) : 0;
		break;
	case SSUSB_UWK_V1_4:
		reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
		msk = WC0_IS_EN_P1_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
		val = enable ? (WC0_IS_EN_P1_95 | WC0_IS_C_95(0x1)) : 0;
		break;
	case SSUSB_UWK_V1_5:
		reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
		msk = WC0_IS_EN_P2_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
		val = enable ? (WC0_IS_EN_P2_95 | WC0_IS_C_95(0x1)) : 0;
		break;
	case SSUSB_UWK_V1_6:
		reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
		msk = WC0_IS_EN_P3_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
		val = enable ? (WC0_IS_EN_P3_95 | WC0_IS_C_95(0x1)) : 0;
		break;
	case SSUSB_UWK_V2:
		reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
		msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;