Commit 43d387a4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2020-08-21' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Regular fixes pull for rc2. Usual rc2 doesn't seem too busy, mainly
  i915 and amdgpu. I'd expect the usual uptick for rc3.

  amdgpu:
   - Fix allocation size
   - SR-IOV fixes
   - Vega20 SMU feature state caching fix
   - Fix custom pptable handling
   - Arcturus golden settings update
   - Several display fixes
   - Fixes for Navy Flounder
   - Misc display fixes
   - RAS fix

  amdkfd:
   - SDMA fix for renoir

  i915:
   - Fix device parameter usage for selftest mock i915 device
   - Fix LPSP capability debugfs NULL dereference
   - Fix buddy register pagemask table
   - Fix intel_atomic_check() non-negative return value
   - Fix selftests passing a random 0 into ilog2()
   - Fix TGL power well enable/disable ordering
   - Switch to PMU module refcounting
   - GVT fixes

  virtio:
   - Add missing dma_fence_put() in virtio_gpu_execbuffer_ioctl()
   - Fix memory leak in virtio_gpu_cleanup_object()"

* tag 'drm-fixes-2020-08-21' of git://anongit.freedesktop.org/drm/drm: (34 commits)
  Revert "drm/amdgpu: disable gfxoff for navy_flounder"
  drm/i915/tgl: Make sure TC-cold is blocked before enabling TC AUX power wells
  drm/i915/selftests: Avoid passing a random 0 into ilog2
  drm/i915: Fix wrong return value in intel_atomic_check()
  drm/i915: Update bw_buddy pagemask table
  drm/i915/display: Check for an LPSP encoder before dereferencing
  drm/i915: Copy default modparams to mock i915_device
  drm/i915: Provide the perf pmu.module
  drm/amd/display: fix pow() crashing when given base 0
  drm/amd/display: Reset scrambling on Test Pattern
  drm/amd/display: fix dcn3 wide timing dsc validation
  drm/amd/display: Fix DFPstate hang due to view port changed
  drm/amd/display: Assign correct left shift
  drm/amd/display: Call DMUB for eDP power control
  drm/amdkfd: fix the wrong sdma instance query for renoir
  drm/amdgpu: parse ta firmware for navy_flounder
  drm/amdgpu: fix NULL pointer access issue when unloading driver
  drm/amdgpu: fix uninit-value in arcturus_log_thermal_throttling_event()
  drm/amdgpu: disable gfxoff for navy_flounder
  drm/amdgpu/display: use GFP_ATOMIC in dcn20_validate_bandwidth_internal
  ...
parents da2968ff 0790e63f

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

+22 −9
Original line number Diff line number Diff line
@@ -195,19 +195,32 @@ static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, 
				unsigned int engine_id,

				unsigned int queue_id)

{

	uint32_t sdma_engine_reg_base[2] = {

		SOC15_REG_OFFSET(SDMA0, 0,

				 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,

		SOC15_REG_OFFSET(SDMA1, 0,

				 mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL

	};

	uint32_t retval = sdma_engine_reg_base[engine_id]

	uint32_t sdma_engine_reg_base = 0;

	uint32_t sdma_rlc_reg_offset;



	switch (engine_id) {

	default:

		dev_warn(adev->dev,

			 "Invalid sdma engine id (%d), using engine id 0\n",

			 engine_id);

		fallthrough;

	case 0:

		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,

				mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;

		break;

	case 1:

		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,

				mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;

		break;

	}



	sdma_rlc_reg_offset = sdma_engine_reg_base

		+ queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);



	pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,

			queue_id, retval);

		 queue_id, sdma_rlc_reg_offset);



	return retval;

	return sdma_rlc_reg_offset;

}



static inline struct v9_mqd *get_mqd(void *mqd)

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+0 −2
Original line number Diff line number Diff line
@@ -1243,7 +1243,6 @@ void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, 
	if (!obj || !obj->ent)

		return;



	debugfs_remove(obj->ent);

	obj->ent = NULL;

	put_obj(obj);

}
@@ -1257,7 +1256,6 @@ static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev) 
		amdgpu_ras_debugfs_remove(adev, &obj->head);

	}



	debugfs_remove_recursive(con->dir);

	con->dir = NULL;

}

/* debugfs end */

drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

+1 −1
Original line number Diff line number Diff line
@@ -462,7 +462,7 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, 
	unsigned int pages;

	int i, r;



	*sgt = kmalloc(sizeof(*sg), GFP_KERNEL);

	*sgt = kmalloc(sizeof(**sgt), GFP_KERNEL);

	if (!*sgt)

		return -ENOMEM;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+1 −0
Original line number Diff line number Diff line
@@ -691,6 +691,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000)

};



static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = {

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

+19 −0
Original line number Diff line number Diff line
@@ -135,6 +135,12 @@ static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev) 
{

	uint32_t tmp;



	/* These registers are not accessible to VF-SRIOV.

	 * The PF will program them instead.

	 */

	if (amdgpu_sriov_vf(adev))

		return;



	/* Setup L2 cache */

	tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);

	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
@@ -190,6 +196,12 @@ static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev) 


static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)

{

	/* These registers are not accessible to VF-SRIOV.

	 * The PF will program them instead.

	 */

	if (amdgpu_sriov_vf(adev))

		return;



	WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,

		     0xFFFFFFFF);

	WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
@@ -326,6 +338,13 @@ void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev, 
					  bool value)

{

	u32 tmp;



	/* These registers are not accessible to VF-SRIOV.

	 * The PF will program them instead.

	 */

	if (amdgpu_sriov_vf(adev))

		return;



	tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);

	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

			    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);