Commit 43ac0b82 authored by Srujana Challa's avatar Srujana Challa Committed by Herbert Xu
Browse files

crypto: octeontx2 - load microcode and create engine groups 



CPT includes microcoded GigaCypher symmetric engines(SEs), IPsec
symmetric engines(IEs), and asymmetric engines (AEs).
Each engine receives CPT instructions from the engine groups it has
subscribed to. This patch loads microcode, configures three engine
groups(one for SEs, one for IEs and one for AEs), and configures
all engines.

Signed-off-by: default avatarSuheil Chandran <schandran@marvell.com>
Signed-off-by: default avatarLukasz Bartosik <lbartosik@marvell.com>
Signed-off-by: default avatarSrujana Challa <schalla@marvell.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent fe16ecea

drivers/crypto/marvell/octeontx2/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -2,6 +2,6 @@ 
obj-$(CONFIG_CRYPTO_DEV_OCTEONTX2_CPT) += octeontx2-cpt.o



octeontx2-cpt-objs := otx2_cptpf_main.o otx2_cptpf_mbox.o \

		      otx2_cpt_mbox_common.o

		      otx2_cpt_mbox_common.o otx2_cptpf_ucode.o



ccflags-y += -I$(srctree)/drivers/net/ethernet/marvell/octeontx2/af

drivers/crypto/marvell/octeontx2/otx2_cpt_common.h

+42 −0
Original line number Diff line number Diff line
@@ -18,6 +18,37 @@ 
#define OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs) \

		(((blk) << 20) | ((slot) << 12) | (offs))



#define OTX2_CPT_INVALID_CRYPTO_ENG_GRP 0xFF

#define OTX2_CPT_NAME_LENGTH 64



#define BAD_OTX2_CPT_ENG_TYPE OTX2_CPT_MAX_ENG_TYPES



enum otx2_cpt_eng_type {

	OTX2_CPT_AE_TYPES = 1,

	OTX2_CPT_SE_TYPES = 2,

	OTX2_CPT_IE_TYPES = 3,

	OTX2_CPT_MAX_ENG_TYPES,

};



/* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */

#define MBOX_MSG_GET_ENG_GRP_NUM        0xBFF



/*

 * Message request and response to get engine group number

 * which has attached a given type of engines (SE, AE, IE)

 * This messages are only used between CPT PF <=> CPT VF

 */

struct otx2_cpt_egrp_num_msg {

	struct mbox_msghdr hdr;

	u8 eng_type;

};



struct otx2_cpt_egrp_num_rsp {

	struct mbox_msghdr hdr;

	u8 eng_type;

	u8 eng_grp_num;

};



static inline void otx2_cpt_write64(void __iomem *reg_base, u64 blk, u64 slot,

				    u64 offs, u64 val)

{
@@ -34,4 +65,15 @@ static inline u64 otx2_cpt_read64(void __iomem *reg_base, u64 blk, u64 slot, 


int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);

int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);



int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox,

				  struct pci_dev *pdev);

int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox,

			     struct pci_dev *pdev, u64 reg, u64 *val);

int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

			      u64 reg, u64 val);

int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

			 u64 reg, u64 *val);

int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

			  u64 reg, u64 val);

#endif /* __OTX2_CPT_COMMON_H */

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

+77 −0
Original line number Diff line number Diff line
@@ -35,3 +35,80 @@ int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev) 


	return otx2_cpt_send_mbox_msg(mbox, pdev);

}



int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox, struct pci_dev *pdev)

{

	return otx2_cpt_send_mbox_msg(mbox, pdev);

}



int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

			     u64 reg, u64 *val)

{

	struct cpt_rd_wr_reg_msg *reg_msg;



	reg_msg = (struct cpt_rd_wr_reg_msg *)

			otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*reg_msg),

						sizeof(*reg_msg));

	if (reg_msg == NULL) {

		dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");

		return -EFAULT;

	}



	reg_msg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;

	reg_msg->hdr.sig = OTX2_MBOX_REQ_SIG;

	reg_msg->hdr.pcifunc = 0;



	reg_msg->is_write = 0;

	reg_msg->reg_offset = reg;

	reg_msg->ret_val = val;



	return 0;

}



int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

			      u64 reg, u64 val)

{

	struct cpt_rd_wr_reg_msg *reg_msg;



	reg_msg = (struct cpt_rd_wr_reg_msg *)

			otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*reg_msg),

						sizeof(*reg_msg));

	if (reg_msg == NULL) {

		dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");

		return -EFAULT;

	}



	reg_msg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;

	reg_msg->hdr.sig = OTX2_MBOX_REQ_SIG;

	reg_msg->hdr.pcifunc = 0;



	reg_msg->is_write = 1;

	reg_msg->reg_offset = reg;

	reg_msg->val = val;



	return 0;

}



int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

			 u64 reg, u64 *val)

{

	int ret;



	ret = otx2_cpt_add_read_af_reg(mbox, pdev, reg, val);

	if (ret)

		return ret;



	return otx2_cpt_send_mbox_msg(mbox, pdev);

}



int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

			  u64 reg, u64 val)

{

	int ret;



	ret = otx2_cpt_add_write_af_reg(mbox, pdev, reg, val);

	if (ret)

		return ret;



	return otx2_cpt_send_mbox_msg(mbox, pdev);

}

drivers/crypto/marvell/octeontx2/otx2_cptpf.h

+3 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#define __OTX2_CPTPF_H



#include "otx2_cpt_common.h"

#include "otx2_cptpf_ucode.h"



struct otx2_cptpf_dev;

struct otx2_cptvf_info {
@@ -27,6 +28,8 @@ struct otx2_cptpf_dev { 
	void __iomem *vfpf_mbox_base;   /* VF-PF mbox start address */

	struct pci_dev *pdev;		/* PCI device handle */

	struct otx2_cptvf_info vf[OTX2_CPT_MAX_VFS_NUM];

	struct otx2_cpt_eng_grps eng_grps;/* Engine groups information */



	/* AF <=> PF mbox */

	struct otx2_mbox	afpf_mbox;

	struct work_struct	afpf_mbox_work;

drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c

+72 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
#include <linux/firmware.h>

#include "otx2_cpt_hw_types.h"

#include "otx2_cpt_common.h"

#include "otx2_cptpf_ucode.h"

#include "otx2_cptpf.h"

#include "rvu_reg.h"
@@ -410,6 +411,59 @@ static int cpt_is_pf_usable(struct otx2_cptpf_dev *cptpf) 
	return 0;

}



static int cptpf_device_reset(struct otx2_cptpf_dev *cptpf)

{

	int timeout = 10, ret;

	u64 reg = 0;



	ret = otx2_cpt_write_af_reg(&cptpf->afpf_mbox, cptpf->pdev,

				    CPT_AF_BLK_RST, 0x1);

	if (ret)

		return ret;



	do {

		ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox, cptpf->pdev,

					   CPT_AF_BLK_RST, &reg);

		if (ret)

			return ret;



		if (!((reg >> 63) & 0x1))

			break;



		usleep_range(10000, 20000);

		if (timeout-- < 0)

			return -EBUSY;

	} while (1);



	return ret;

}



static int cptpf_device_init(struct otx2_cptpf_dev *cptpf)

{

	union otx2_cptx_af_constants1 af_cnsts1 = {0};

	int ret = 0;



	/* Reset the CPT PF device */

	ret = cptpf_device_reset(cptpf);

	if (ret)

		return ret;



	/* Get number of SE, IE and AE engines */

	ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox, cptpf->pdev,

				   CPT_AF_CONSTANTS1, &af_cnsts1.u);

	if (ret)

		return ret;



	cptpf->eng_grps.avail.max_se_cnt = af_cnsts1.s.se;

	cptpf->eng_grps.avail.max_ie_cnt = af_cnsts1.s.ie;

	cptpf->eng_grps.avail.max_ae_cnt = af_cnsts1.s.ae;



	/* Disable all cores */

	ret = otx2_cpt_disable_all_cores(cptpf);



	return ret;

}



static int cptpf_sriov_disable(struct pci_dev *pdev)

{

	struct otx2_cptpf_dev *cptpf = pci_get_drvdata(pdev);
@@ -446,6 +500,10 @@ static int cptpf_sriov_enable(struct pci_dev *pdev, int num_vfs) 
	if (ret)

		goto destroy_flr;



	ret = otx2_cpt_create_eng_grps(cptpf->pdev, &cptpf->eng_grps);

	if (ret)

		goto disable_intr;



	cptpf->enabled_vfs = num_vfs;

	ret = pci_enable_sriov(pdev, num_vfs);

	if (ret)
@@ -543,8 +601,20 @@ static int otx2_cptpf_probe(struct pci_dev *pdev, 


	cptpf->max_vfs = pci_sriov_get_totalvfs(pdev);



	/* Initialize CPT PF device */

	err = cptpf_device_init(cptpf);

	if (err)

		goto unregister_intr;



	/* Initialize engine groups */

	err = otx2_cpt_init_eng_grps(pdev, &cptpf->eng_grps);

	if (err)

		goto unregister_intr;



	return 0;



unregister_intr:

	cptpf_disable_afpf_mbox_intr(cptpf);

destroy_afpf_mbox:

	cptpf_afpf_mbox_destroy(cptpf);

clear_drvdata:
@@ -560,6 +630,8 @@ static void otx2_cptpf_remove(struct pci_dev *pdev) 
		return;



	cptpf_sriov_disable(pdev);

	/* Cleanup engine groups */

	otx2_cpt_cleanup_eng_grps(pdev, &cptpf->eng_grps);

	/* Disable AF-PF mailbox interrupt */

	cptpf_disable_afpf_mbox_intr(cptpf);

	/* Destroy AF-PF mbox */