Commit 43aa755e authored by Zhanjun Dong's avatar Zhanjun Dong Committed by Daniele Ceraolo Spurio
Browse files

drm/i915/mtl: Update cache coherency setting for context structure 



As context structure is shared memory for CPU/GPU, Wa_22016122933 is
needed for this memory block as well.

Signed-off-by: default avatarZhanjun Dong <zhanjun.dong@intel.com>
CC: Fei Yang <fei.yang@intel.com>
Reviewed-by: default avatarFei Yang <fei.yang@intel.com>
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230706174704.177929-1-zhanjun.dong@intel.com
parent 2f42c5af

drivers/gpu/drm/i915/gt/intel_lrc.c

+8 −1
Original line number Diff line number Diff line
@@ -1092,8 +1092,15 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine) 


	obj = i915_gem_object_create_lmem(engine->i915, context_size,

					  I915_BO_ALLOC_PM_VOLATILE);

	if (IS_ERR(obj))

	if (IS_ERR(obj)) {

		obj = i915_gem_object_create_shmem(engine->i915, context_size);

		/*

		 * Wa_22016122933: For MTL the shared memory needs to be mapped

		 * as WC on CPU side and UC (PAT index 2) on GPU side

		 */

		if (IS_METEORLAKE(engine->i915))

			i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);

	}

	if (IS_ERR(obj))

		return ERR_CAST(obj);