Unverified Commit 43a03d24 authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Mark Brown
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ASoC: SOF: Intel: hda-loader: Use the FSR state definitions during bootup 



Switch to use the newly added FSR (Firmware State Register) definitions
for DSP state handling and targeting.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarRander Wang <rander.wang@intel.com>
Reviewed-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220712125734.30512-3-peter.ujfalusi@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 94f07274

sound/soc/sof/intel/hda-loader.c

+4 −6
Original line number Diff line number Diff line
@@ -177,14 +177,13 @@ int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot) 
	 * - IMR boot: wait for ROM firmware entered (firmware booted up from IMR)

	 */

	if (imr_boot)

		target_status = HDA_DSP_ROM_FW_ENTERED;

		target_status = FSR_STATE_FW_ENTERED;

	else

		target_status = HDA_DSP_ROM_INIT;

		target_status = FSR_STATE_INIT_DONE;



	ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,

					chip->rom_status_reg, status,

					((status & HDA_DSP_ROM_STS_MASK)

						== target_status),

					(FSR_TO_STATE_CODE(status) == target_status),

					HDA_DSP_REG_POLL_INTERVAL_US,

					chip->rom_init_timeout *

					USEC_PER_MSEC);
@@ -292,8 +291,7 @@ int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream 


	status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,

					chip->rom_status_reg, reg,

					((reg & HDA_DSP_ROM_STS_MASK)

						== HDA_DSP_ROM_FW_ENTERED),

					(FSR_TO_STATE_CODE(reg) == FSR_STATE_FW_ENTERED),

					HDA_DSP_REG_POLL_INTERVAL_US,

					HDA_DSP_BASEFW_TIMEOUT_US);