Commit 438b8dc9 authored by Vignesh Raghavendra's avatar Vignesh Raghavendra Committed by Nishanth Menon
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arm64: dts: ti: k3-am62a7: Correct L2 cache size to 512KB 

Per AM62Ax SoC datasheet[0] L2 cache is 512KB.

[0] https://www.ti.com/lit/gpn/am62a7

 Page 1.

Fixes: 5fc6b1b6 ("arm64: dts: ti: Introduce AM62A7 family of SoCs")
Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230320044935.2512288-2-vigneshr@ti.com


Signed-off-by: default avatarNishanth Menon <nm@ti.com>
parent 6974371c

arch/arm64/boot/dts/ti/k3-am62a7.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -97,7 +97,7 @@ 
		compatible = "cache";

		cache-unified;

		cache-level = <2>;

		cache-size = <0x40000>;

		cache-size = <0x80000>;

		cache-line-size = <64>;

		cache-sets = <512>;

	};