Commit 432b0966 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-5.20-1' of... 

Merge tag 'sunxi-clk-for-5.20-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Jernej Skrabec:

 - deduplicate Allwinner ccu_clks arrays
 - Allwinner H6 GPU DFS support
 - adjust Allwinner Kconfig

* tag 'sunxi-clk-for-5.20-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS
  clk: sunxi: Do not select the PRCM MFD
  clk: sunxi: Limit legacy clocks to 32-bit ARM
  clk: sunxi-ng: Deduplicate ccu_clks arrays
parents f2906aa8 4167ac8a

drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c

+3 −13
Original line number Diff line number Diff line
@@ -138,19 +138,9 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = { 
	&r_apb2_rsb_clk.common,

	&r_apb1_ir_clk.common,

	&r_apb1_w1_clk.common,

	&ir_clk.common,

	&w1_clk.common,

};



static struct ccu_common *sun50i_h616_r_ccu_clks[] = {

	&r_apb1_clk.common,

	&r_apb2_clk.common,

	&r_apb1_twd_clk.common,

	&r_apb2_i2c_clk.common,

	&r_apb2_rsb_clk.common,

	&r_apb1_ir_clk.common,

	&r_apb1_rtc_clk.common,

	&ir_clk.common,

	&w1_clk.common,

};



static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
@@ -218,8 +208,8 @@ static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = { 
};



static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {

	.ccu_clks	= sun50i_h616_r_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun50i_h616_r_ccu_clks),

	.ccu_clks	= sun50i_h6_r_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun50i_h6_r_ccu_clks),



	.hw_clks	= &sun50i_h616_r_hw_clks,

drivers/clk/sunxi-ng/ccu-sun50i-h6.c

+13 −3
Original line number Diff line number Diff line
@@ -95,13 +95,13 @@ static struct ccu_nkmp pll_periph1_clk = { 
	},

};



/* For GPU PLL, using an output divider for DFS causes system to fail */

#define SUN50I_H6_PLL_GPU_REG		0x030

static struct ccu_nkmp pll_gpu_clk = {

	.enable		= BIT(31),

	.lock		= BIT(28),

	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),

	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */

	.p		= _SUNXI_CCU_DIV(0, 1), /* output divider */

	.common		= {

		.reg		= 0x030,

		.hw.init	= CLK_HW_INIT("pll-gpu", "osc24M",
@@ -294,9 +294,9 @@ static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", 
static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",

		      0x62c, BIT(0), 0);



/* Keep GPU_CLK divider const to avoid DFS instability. */

static const char * const gpu_parents[] = { "pll-gpu" };

static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,

				       0, 3,	/* M */

static SUNXI_CCU_MUX_WITH_GATE(gpu_clk, "gpu", gpu_parents, 0x670,

				       24, 1,	/* mux */

				       BIT(31),	/* gate */

				       CLK_SET_RATE_PARENT);
@@ -1191,6 +1191,16 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev) 
	if (IS_ERR(reg))

		return PTR_ERR(reg);



	/* Force PLL_GPU output divider bits to 0 */

	val = readl(reg + SUN50I_H6_PLL_GPU_REG);

	val &= ~BIT(0);

	writel(val, reg + SUN50I_H6_PLL_GPU_REG);



	/* Force GPU_CLK divider bits to 0 */

	val = readl(reg + gpu_clk.common.reg);

	val &= ~GENMASK(3, 0);

	writel(val, reg + gpu_clk.common.reg);



	/* Enable the lock bits on all PLLs */

	for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {

		val = readl(reg + pll_regs[i]);

drivers/clk/sunxi-ng/ccu-sun8i-de2.c

+19 −58
Original line number Diff line number Diff line
@@ -53,65 +53,26 @@ static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4, 
static SUNXI_CCU_M(rot_div_a83_clk, "rot-div", "pll-de", 0x0c, 0x0c, 4,

		   CLK_SET_RATE_PARENT);



static struct ccu_common *sun8i_a83t_de2_clks[] = {

static struct ccu_common *sun8i_de2_ccu_clks[] = {

	&mixer0_clk.common,

	&mixer1_clk.common,

	&wb_clk.common,



	&bus_mixer0_clk.common,

	&bus_mixer1_clk.common,

	&bus_wb_clk.common,



	&mixer0_div_a83_clk.common,

	&mixer1_div_a83_clk.common,

	&wb_div_a83_clk.common,



	&bus_rot_clk.common,

	&rot_clk.common,

	&rot_div_a83_clk.common,

};



static struct ccu_common *sun8i_h3_de2_clks[] = {

	&mixer0_clk.common,

	&mixer1_clk.common,

	&wb_clk.common,



	&bus_mixer0_clk.common,

	&bus_mixer1_clk.common,

	&bus_wb_clk.common,



	&mixer0_div_clk.common,

	&mixer1_div_clk.common,

	&wb_div_clk.common,

};



static struct ccu_common *sun8i_v3s_de2_clks[] = {

	&mixer0_clk.common,

	&wb_clk.common,



	&bus_mixer0_clk.common,

	&bus_wb_clk.common,



	&mixer0_div_clk.common,

	&wb_div_clk.common,

};



static struct ccu_common *sun50i_a64_de2_clks[] = {

	&mixer0_clk.common,

	&mixer1_clk.common,

	&wb_clk.common,



	&bus_mixer0_clk.common,

	&bus_mixer1_clk.common,

	&bus_wb_clk.common,

	&bus_rot_clk.common,



	&mixer0_div_clk.common,

	&mixer1_div_clk.common,

	&wb_div_clk.common,



	&bus_rot_clk.common,

	&rot_clk.common,

	&rot_div_clk.common,



	&mixer0_div_a83_clk.common,

	&mixer1_div_a83_clk.common,

	&wb_div_a83_clk.common,

	&rot_div_a83_clk.common,

};



static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
@@ -219,8 +180,8 @@ static struct ccu_reset_map sun50i_h5_de2_resets[] = { 
};



static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {

	.ccu_clks	= sun8i_a83t_de2_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun8i_a83t_de2_clks),

	.ccu_clks	= sun8i_de2_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun8i_de2_ccu_clks),



	.hw_clks	= &sun8i_a83t_de2_hw_clks,
@@ -229,8 +190,8 @@ static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = { 
};



static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {

	.ccu_clks	= sun8i_h3_de2_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_de2_clks),

	.ccu_clks	= sun8i_de2_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun8i_de2_ccu_clks),



	.hw_clks	= &sun8i_h3_de2_hw_clks,
@@ -239,8 +200,8 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = { 
};



static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {

	.ccu_clks	= sun50i_a64_de2_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun50i_a64_de2_clks),

	.ccu_clks	= sun8i_de2_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun8i_de2_ccu_clks),



	.hw_clks	= &sun50i_a64_de2_hw_clks,
@@ -249,8 +210,8 @@ static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = { 
};



static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {

	.ccu_clks	= sun8i_v3s_de2_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun8i_v3s_de2_clks),

	.ccu_clks	= sun8i_de2_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun8i_de2_ccu_clks),



	.hw_clks	= &sun8i_v3s_de2_hw_clks,
@@ -259,8 +220,8 @@ static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = { 
};



static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {

	.ccu_clks	= sun50i_a64_de2_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun50i_a64_de2_clks),

	.ccu_clks	= sun8i_de2_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun8i_de2_ccu_clks),



	.hw_clks	= &sun50i_a64_de2_hw_clks,
@@ -269,8 +230,8 @@ static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = { 
};



static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {

	.ccu_clks	= sun8i_h3_de2_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_de2_clks),

	.ccu_clks	= sun8i_de2_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun8i_de2_ccu_clks),



	.hw_clks	= &sun8i_h3_de2_hw_clks,

drivers/clk/sunxi-ng/ccu-sun8i-h3.c

+3 −110
Original line number Diff line number Diff line
@@ -562,6 +562,7 @@ static struct ccu_common *sun8i_h3_ccu_clks[] = { 
	&bus_uart2_clk.common,

	&bus_uart3_clk.common,

	&bus_scr0_clk.common,

	&bus_scr1_clk.common,

	&bus_ephy_clk.common,

	&bus_dbg_clk.common,

	&ths_clk.common,
@@ -612,114 +613,6 @@ static struct ccu_common *sun8i_h3_ccu_clks[] = { 
	&gpu_clk.common,

};



static struct ccu_common *sun50i_h5_ccu_clks[] = {

	&pll_cpux_clk.common,

	&pll_audio_base_clk.common,

	&pll_video_clk.common,

	&pll_ve_clk.common,

	&pll_ddr_clk.common,

	&pll_periph0_clk.common,

	&pll_gpu_clk.common,

	&pll_periph1_clk.common,

	&pll_de_clk.common,

	&cpux_clk.common,

	&axi_clk.common,

	&ahb1_clk.common,

	&apb1_clk.common,

	&apb2_clk.common,

	&ahb2_clk.common,

	&bus_ce_clk.common,

	&bus_dma_clk.common,

	&bus_mmc0_clk.common,

	&bus_mmc1_clk.common,

	&bus_mmc2_clk.common,

	&bus_nand_clk.common,

	&bus_dram_clk.common,

	&bus_emac_clk.common,

	&bus_ts_clk.common,

	&bus_hstimer_clk.common,

	&bus_spi0_clk.common,

	&bus_spi1_clk.common,

	&bus_otg_clk.common,

	&bus_ehci0_clk.common,

	&bus_ehci1_clk.common,

	&bus_ehci2_clk.common,

	&bus_ehci3_clk.common,

	&bus_ohci0_clk.common,

	&bus_ohci1_clk.common,

	&bus_ohci2_clk.common,

	&bus_ohci3_clk.common,

	&bus_ve_clk.common,

	&bus_tcon0_clk.common,

	&bus_tcon1_clk.common,

	&bus_deinterlace_clk.common,

	&bus_csi_clk.common,

	&bus_tve_clk.common,

	&bus_hdmi_clk.common,

	&bus_de_clk.common,

	&bus_gpu_clk.common,

	&bus_msgbox_clk.common,

	&bus_spinlock_clk.common,

	&bus_codec_clk.common,

	&bus_spdif_clk.common,

	&bus_pio_clk.common,

	&bus_ths_clk.common,

	&bus_i2s0_clk.common,

	&bus_i2s1_clk.common,

	&bus_i2s2_clk.common,

	&bus_i2c0_clk.common,

	&bus_i2c1_clk.common,

	&bus_i2c2_clk.common,

	&bus_uart0_clk.common,

	&bus_uart1_clk.common,

	&bus_uart2_clk.common,

	&bus_uart3_clk.common,

	&bus_scr0_clk.common,

	&bus_scr1_clk.common,

	&bus_ephy_clk.common,

	&bus_dbg_clk.common,

	&ths_clk.common,

	&nand_clk.common,

	&mmc0_clk.common,

	&mmc1_clk.common,

	&mmc2_clk.common,

	&ts_clk.common,

	&ce_clk.common,

	&spi0_clk.common,

	&spi1_clk.common,

	&i2s0_clk.common,

	&i2s1_clk.common,

	&i2s2_clk.common,

	&spdif_clk.common,

	&usb_phy0_clk.common,

	&usb_phy1_clk.common,

	&usb_phy2_clk.common,

	&usb_phy3_clk.common,

	&usb_ohci0_clk.common,

	&usb_ohci1_clk.common,

	&usb_ohci2_clk.common,

	&usb_ohci3_clk.common,

	&dram_clk.common,

	&dram_ve_clk.common,

	&dram_csi_clk.common,

	&dram_deinterlace_clk.common,

	&dram_ts_clk.common,

	&de_clk.common,

	&tcon_clk.common,

	&tve_clk.common,

	&deinterlace_clk.common,

	&csi_misc_clk.common,

	&csi_sclk_clk.common,

	&csi_mclk_clk.common,

	&ve_clk.common,

	&ac_dig_clk.common,

	&avs_clk.common,

	&hdmi_clk.common,

	&hdmi_ddc_clk.common,

	&mbus_clk.common,

	&gpu_clk.common,

};



static const struct clk_hw *clk_parent_pll_audio[] = {

	&pll_audio_base_clk.common.hw

};
@@ -1116,8 +1009,8 @@ static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = { 
};



static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {

	.ccu_clks	= sun50i_h5_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun50i_h5_ccu_clks),

	.ccu_clks	= sun8i_h3_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_ccu_clks),



	.hw_clks	= &sun50i_h5_hw_clks,

drivers/clk/sunxi-ng/ccu-sun8i-r.c

+8 −32
Original line number Diff line number Diff line
@@ -114,32 +114,7 @@ static struct ccu_mp a83t_ir_clk = { 
	},

};



static struct ccu_common *sun8i_a83t_r_ccu_clks[] = {

	&ar100_clk.common,

	&apb0_clk.common,

	&apb0_pio_clk.common,

	&apb0_ir_clk.common,

	&apb0_timer_clk.common,

	&apb0_rsb_clk.common,

	&apb0_uart_clk.common,

	&apb0_i2c_clk.common,

	&apb0_twd_clk.common,

	&a83t_ir_clk.common,

};



static struct ccu_common *sun8i_h3_r_ccu_clks[] = {

	&ar100_clk.common,

	&apb0_clk.common,

	&apb0_pio_clk.common,

	&apb0_ir_clk.common,

	&apb0_timer_clk.common,

	&apb0_uart_clk.common,

	&apb0_i2c_clk.common,

	&apb0_twd_clk.common,

	&ir_clk.common,

};



static struct ccu_common *sun50i_a64_r_ccu_clks[] = {

static struct ccu_common *sun8i_r_ccu_clks[] = {

	&ar100_clk.common,

	&apb0_clk.common,

	&apb0_pio_clk.common,
@@ -150,6 +125,7 @@ static struct ccu_common *sun50i_a64_r_ccu_clks[] = { 
	&apb0_i2c_clk.common,

	&apb0_twd_clk.common,

	&ir_clk.common,

	&a83t_ir_clk.common,

};



static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = {
@@ -226,8 +202,8 @@ static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = { 
};



static const struct sunxi_ccu_desc sun8i_a83t_r_ccu_desc = {

	.ccu_clks	= sun8i_a83t_r_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun8i_a83t_r_ccu_clks),

	.ccu_clks	= sun8i_r_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun8i_r_ccu_clks),



	.hw_clks	= &sun8i_a83t_r_hw_clks,
@@ -236,8 +212,8 @@ static const struct sunxi_ccu_desc sun8i_a83t_r_ccu_desc = { 
};



static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = {

	.ccu_clks	= sun8i_h3_r_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_r_ccu_clks),

	.ccu_clks	= sun8i_r_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun8i_r_ccu_clks),



	.hw_clks	= &sun8i_h3_r_hw_clks,
@@ -246,8 +222,8 @@ static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = { 
};



static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = {

	.ccu_clks	= sun50i_a64_r_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun50i_a64_r_ccu_clks),

	.ccu_clks	= sun8i_r_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun8i_r_ccu_clks),



	.hw_clks	= &sun50i_a64_r_hw_clks,