Commit 42e405f7 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'linus' into sched/urgent, to pick up dependencies 



Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents e9532e69 710d60cb

Documentation/DocBook/media/v4l/media-types.xml

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@@ -56,10 +56,6 @@ 
	    <entry><constant>MEDIA_ENT_F_CONN_COMPOSITE</constant></entry>

	    <entry>Connector for a RGB composite signal.</entry>

	  </row>

	  <row>

	    <entry><constant>MEDIA_ENT_F_CONN_TEST</constant></entry>

	    <entry>Connector for a test generator.</entry>

	  </row>

	  <row>

	    <entry><constant>MEDIA_ENT_F_CAM_SENSOR</constant></entry>

	    <entry>Camera video sensor entity.</entry>

Documentation/devicetree/bindings/arm/omap/omap.txt

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@@ -23,6 +23,7 @@ Optional properties: 
  during suspend.

- ti,no-reset-on-init: When present, the module should not be reset at init

- ti,no-idle-on-init: When present, the module should not be idled at init

- ti,no-idle: When present, the module is never allowed to idle.



Example:

Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt

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Alpine MSIX controller



See arm,gic-v3.txt for SPI and MSI definitions.



Required properties:



- compatible: should be "al,alpine-msix"

- reg: physical base address and size of the registers

- interrupt-parent: specifies the parent interrupt controller.

- interrupt-controller: identifies the node as an interrupt controller

- msi-controller: identifies the node as an PCI Message Signaled Interrupt

		  controller

- al,msi-base-spi: SPI base of the MSI frame

- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0



Example:



msix: msix {

	compatible = "al,alpine-msix";

	reg = <0x0 0xfbe00000 0x0 0x100000>;

	interrupt-parent = <&gic>;

	interrupt-controller;

	msi-controller;

	al,msi-base-spi = <160>;

	al,msi-num-spis = <160>;

};

Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt

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@@ -16,6 +16,7 @@ Main node required properties: 
	"arm,cortex-a15-gic"

	"arm,cortex-a7-gic"

	"arm,cortex-a9-gic"

	"arm,eb11mp-gic"

	"arm,gic-400"

	"arm,pl390"

	"arm,tc11mp-gic"

Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt

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* Marvell ODMI for MSI support



Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller

which can be used by on-board peripheral for MSI interrupts.



Required properties:



- compatible           : The value here should contain:



    "marvell,ap806-odmi-controller", "marvell,odmi-controller".



- interrupt,controller : Identifies the node as an interrupt controller.



- msi-controller       : Identifies the node as an MSI controller.



- marvell,odmi-frames  : Number of ODMI frames available. Each frame

                         provides a number of events.



- reg                  : List of register definitions, one for each

                         ODMI frame.



- marvell,spi-base     : List of GIC base SPI interrupts, one for each

                         ODMI frame. Those SPI interrupts are 0-based,

                         i.e marvell,spi-base = <128> will use SPI #96.

                         See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt

                         for details about the GIC Device Tree binding.



- interrupt-parent     : Reference to the parent interrupt controller.



Example:



	odmi: odmi@300000 {

		compatible = "marvell,ap806-odm-controller",

			     "marvell,odmi-controller";

		interrupt-controller;

		msi-controller;

		marvell,odmi-frames = <4>;

		reg = <0x300000 0x4000>,

		      <0x304000 0x4000>,

		      <0x308000 0x4000>,

		      <0x30C000 0x4000>;

		marvell,spi-base = <128>, <136>, <144>, <152>;

	};