Commit 42dcd054 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Heiko Stuebner
Browse files

arm64: dts: rockchip: add missing cache properties 



As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:

  rk3588s-khadas-edge2.dtb: l3-cache: 'cache-unified' is a dependency of 'cache-size'

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230421223149.115185-1-krzysztof.kozlowski@linaro.org


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 03633c4e

arch/arm64/boot/dts/rockchip/rk3308.dtsi

+1 −0
Original line number Original line Diff line number Diff line
@@ -97,6 +97,7 @@ 
		l2: l2-cache {

		l2: l2-cache {

			compatible = "cache";

			compatible = "cache";

			cache-level = <2>;

			cache-level = <2>;

			cache-unified;

		};

		};

	};

	};

arch/arm64/boot/dts/rockchip/rk3328.dtsi

+1 −0
Original line number Original line Diff line number Diff line
@@ -103,6 +103,7 @@ 
		l2: l2-cache0 {

		l2: l2-cache0 {

			compatible = "cache";

			compatible = "cache";

			cache-level = <2>;

			cache-level = <2>;

			cache-unified;

		};

		};

	};

	};

arch/arm64/boot/dts/rockchip/rk3588s.dtsi

+9 −0
Original line number Original line Diff line number Diff line
@@ -229,6 +229,7 @@ 
			cache-line-size = <64>;

			cache-line-size = <64>;

			cache-sets = <512>;

			cache-sets = <512>;

			cache-level = <2>;

			cache-level = <2>;

			cache-unified;

			next-level-cache = <&l3_cache>;

			next-level-cache = <&l3_cache>;

		};

		};
@@ -238,6 +239,7 @@ 
			cache-line-size = <64>;

			cache-line-size = <64>;

			cache-sets = <512>;

			cache-sets = <512>;

			cache-level = <2>;

			cache-level = <2>;

			cache-unified;

			next-level-cache = <&l3_cache>;

			next-level-cache = <&l3_cache>;

		};

		};
@@ -247,6 +249,7 @@ 
			cache-line-size = <64>;

			cache-line-size = <64>;

			cache-sets = <512>;

			cache-sets = <512>;

			cache-level = <2>;

			cache-level = <2>;

			cache-unified;

			next-level-cache = <&l3_cache>;

			next-level-cache = <&l3_cache>;

		};

		};
@@ -256,6 +259,7 @@ 
			cache-line-size = <64>;

			cache-line-size = <64>;

			cache-sets = <512>;

			cache-sets = <512>;

			cache-level = <2>;

			cache-level = <2>;

			cache-unified;

			next-level-cache = <&l3_cache>;

			next-level-cache = <&l3_cache>;

		};

		};
@@ -265,6 +269,7 @@ 
			cache-line-size = <64>;

			cache-line-size = <64>;

			cache-sets = <1024>;

			cache-sets = <1024>;

			cache-level = <2>;

			cache-level = <2>;

			cache-unified;

			next-level-cache = <&l3_cache>;

			next-level-cache = <&l3_cache>;

		};

		};
@@ -274,6 +279,7 @@ 
			cache-line-size = <64>;

			cache-line-size = <64>;

			cache-sets = <1024>;

			cache-sets = <1024>;

			cache-level = <2>;

			cache-level = <2>;

			cache-unified;

			next-level-cache = <&l3_cache>;

			next-level-cache = <&l3_cache>;

		};

		};
@@ -283,6 +289,7 @@ 
			cache-line-size = <64>;

			cache-line-size = <64>;

			cache-sets = <1024>;

			cache-sets = <1024>;

			cache-level = <2>;

			cache-level = <2>;

			cache-unified;

			next-level-cache = <&l3_cache>;

			next-level-cache = <&l3_cache>;

		};

		};
@@ -292,6 +299,7 @@ 
			cache-line-size = <64>;

			cache-line-size = <64>;

			cache-sets = <1024>;

			cache-sets = <1024>;

			cache-level = <2>;

			cache-level = <2>;

			cache-unified;

			next-level-cache = <&l3_cache>;

			next-level-cache = <&l3_cache>;

		};

		};
@@ -301,6 +309,7 @@ 
			cache-line-size = <64>;

			cache-line-size = <64>;

			cache-sets = <4096>;

			cache-sets = <4096>;

			cache-level = <3>;

			cache-level = <3>;

			cache-unified;

		};

		};

	};

	};