Commit 42d6e167 authored by Alexandre Courbot's avatar Alexandre Courbot Committed by Ben Skeggs
Browse files

drm/nouveau/clk/gk20a: share reusable structures/functions 



Make functions/structures that the GM20B driver will reuse public.

Signed-off-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 6871b34a

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c

+8 −36
Original line number Diff line number Diff line
@@ -22,8 +22,8 @@ 
 * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c

 *

 */

#define gk20a_clk(p) container_of((p), struct gk20a_clk, base)

#include "priv.h"

#include "gk20a.h"



#include <core/tegra.h>

#include <subdev/timer.h>
@@ -33,9 +33,6 @@ 


#define MASK(w)	((1 << w) - 1)



#define SYS_GPCPLL_CFG_BASE			0x00137000

#define GPC_BCASE_GPCPLL_CFG_BASE		0x00132800



#define GPCPLL_CFG		(SYS_GPCPLL_CFG_BASE + 0)

#define GPCPLL_CFG_ENABLE	BIT(0)

#define GPCPLL_CFG_IDDQ		BIT(1)
@@ -57,6 +54,7 @@ 
#define GPCPLL_CFG3			(SYS_GPCPLL_CFG_BASE + 0x18)

#define GPCPLL_CFG3_PLL_STEPB_SHIFT	16



#define GPC_BCASE_GPCPLL_CFG_BASE		0x00132800

#define GPCPLL_NDIV_SLOWDOWN			(SYS_GPCPLL_CFG_BASE + 0x1c)

#define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT	0

#define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT	8
@@ -98,14 +96,6 @@ static const u8 _pl_to_div[] = { 
/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32,

};



/* All frequencies in Khz */

struct gk20a_clk_pllg_params {

	u32 min_vco, max_vco;

	u32 min_u, max_u;

	u32 min_m, max_m;

	u32 min_n, max_n;

	u32 min_pl, max_pl;

};

static u32 pl_to_div(u32 pl)

{

	if (pl >= ARRAY_SIZE(_pl_to_div))
@@ -134,22 +124,6 @@ static const struct gk20a_clk_pllg_params gk20a_pllg_params = { 
	.min_pl = 1, .max_pl = 32,

};



struct gk20a_pll {

	u32 m;

	u32 n;

	u32 pl;

};



struct gk20a_clk {

	struct nvkm_clk base;

	const struct gk20a_clk_pllg_params *params;

	struct gk20a_pll pll;

	u32 parent_rate;



	u32 (*div_to_pl)(u32);

	u32 (*pl_to_div)(u32);

};



static void

gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll)

{
@@ -472,8 +446,6 @@ gk20a_pllg_program_mnp(struct gk20a_clk *clk) 
	return err;

}



#define GK20A_CLK_GPC_MDIV 1000



static struct nvkm_pstate

gk20a_pstates[] = {

	{
@@ -568,7 +540,7 @@ gk20a_pstates[] = { 
	},

};



static int

int

gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src)

{

	struct gk20a_clk *clk = gk20a_clk(base);
@@ -587,7 +559,7 @@ gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src) 
	}

}



static int

int

gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)

{

	struct gk20a_clk *clk = gk20a_clk(base);
@@ -596,7 +568,7 @@ gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) 
					 GK20A_CLK_GPC_MDIV);

}



static int

int

gk20a_clk_prog(struct nvkm_clk *base)

{

	struct gk20a_clk *clk = gk20a_clk(base);
@@ -604,12 +576,12 @@ gk20a_clk_prog(struct nvkm_clk *base) 
	return gk20a_pllg_program_mnp(clk);

}



static void

void

gk20a_clk_tidy(struct nvkm_clk *base)

{

}



static void

void

gk20a_clk_fini(struct nvkm_clk *base)

{

	struct nvkm_device *device = base->subdev.device;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h

0 → 100644
+65 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef __NVKM_CLK_GK20A_H__

#define __NVKM_CLK_GK20A_H__



#define GK20A_CLK_GPC_MDIV 1000



#define SYS_GPCPLL_CFG_BASE	0x00137000



/* All frequencies in Khz */

struct gk20a_clk_pllg_params {

	u32 min_vco, max_vco;

	u32 min_u, max_u;

	u32 min_m, max_m;

	u32 min_n, max_n;

	u32 min_pl, max_pl;

};



struct gk20a_pll {

	u32 m;

	u32 n;

	u32 pl;

};



struct gk20a_clk {

	struct nvkm_clk base;

	const struct gk20a_clk_pllg_params *params;

	struct gk20a_pll pll;

	u32 parent_rate;



	u32 (*div_to_pl)(u32);

	u32 (*pl_to_div)(u32);

};

#define gk20a_clk(p) container_of((p), struct gk20a_clk, base)



int _gk20a_clk_ctor(struct nvkm_device *, int, const struct nvkm_clk_func *,

		    const struct gk20a_clk_pllg_params *, struct gk20a_clk *);

void gk20a_clk_fini(struct nvkm_clk *);

int gk20a_clk_read(struct nvkm_clk *, enum nv_clk_src);

int gk20a_clk_calc(struct nvkm_clk *, struct nvkm_cstate *);

int gk20a_clk_prog(struct nvkm_clk *);

void gk20a_clk_tidy(struct nvkm_clk *);



#endif