Commit 42c88ff8 authored by Sean Christopherson's avatar Sean Christopherson Committed by Paolo Bonzini
Browse files

KVM: x86/mmu: Dedup macros for computing various page table masks 



Provide common helper macros to generate various masks, shifts, etc...
for 32-bit vs. 64-bit page tables.  Only the inputs differ, the actual
calculations are identical.

No functional change intended.

Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
Message-Id: <20220614233328.3896033-5-seanjc@google.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent b3fcdb04

arch/x86/kvm/mmu.h

+2 −2
Original line number Diff line number Diff line
@@ -7,9 +7,9 @@ 
#include "cpuid.h"



#define PT64_PT_BITS 9

#define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)

#define PT64_ENT_PER_PAGE __PT_ENT_PER_PAGE(PT64_PT_BITS)

#define PT32_PT_BITS 10

#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)

#define PT32_ENT_PER_PAGE __PT_ENT_PER_PAGE(PT32_PT_BITS)



#define PT_WRITABLE_SHIFT 1

#define PT_USER_SHIFT 2

arch/x86/kvm/mmu/mmu.c

+5 −9
Original line number Diff line number Diff line
@@ -113,21 +113,17 @@ module_param(dbg, bool, 0644); 


#define PT32_LEVEL_BITS 10



#define PT32_LEVEL_SHIFT(level) \

		(PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)

#define PT32_LEVEL_SHIFT(level) __PT_LEVEL_SHIFT(level, PT32_LEVEL_BITS)



#define PT32_LVL_OFFSET_MASK(level) \

	(PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \

						* PT32_LEVEL_BITS))) - 1))



#define PT32_INDEX(address, level)\

	(((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))

	__PT_LVL_OFFSET_MASK(PT32_BASE_ADDR_MASK, level, PT32_LEVEL_BITS)



#define PT32_INDEX(address, level) __PT_INDEX(address, level, PT32_LEVEL_BITS)



#define PT32_BASE_ADDR_MASK PAGE_MASK



#define PT32_LVL_ADDR_MASK(level) \

	(PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \

					    * PT32_LEVEL_BITS))) - 1))

	__PT_LVL_ADDR_MASK(PT32_BASE_ADDR_MASK, level, PT32_LEVEL_BITS)



#include <trace/events/kvm.h>

arch/x86/kvm/mmu/mmu_internal.h

+14 −0
Original line number Diff line number Diff line
@@ -20,6 +20,20 @@ extern bool dbg; 
#define MMU_WARN_ON(x) do { } while (0)

#endif



/* Page table builder macros common to shadow (host) PTEs and guest PTEs. */

#define __PT_LEVEL_SHIFT(level, bits_per_level)	\

	(PAGE_SHIFT + ((level) - 1) * (bits_per_level))

#define __PT_INDEX(address, level, bits_per_level) \

	(((address) >> __PT_LEVEL_SHIFT(level, bits_per_level)) & ((1 << (bits_per_level)) - 1))



#define __PT_LVL_ADDR_MASK(base_addr_mask, level, bits_per_level) \

	((base_addr_mask) & ~((1ULL << (PAGE_SHIFT + (((level) - 1) * (bits_per_level)))) - 1))



#define __PT_LVL_OFFSET_MASK(base_addr_mask, level, bits_per_level) \

	((base_addr_mask) & ((1ULL << (PAGE_SHIFT + (((level) - 1) * (bits_per_level)))) - 1))



#define __PT_ENT_PER_PAGE(bits_per_level)  (1 << (bits_per_level))



/*

 * Unlike regular MMU roots, PAE "roots", a.k.a. PDPTEs/PDPTRs, have a PRESENT

 * bit, and thus are guaranteed to be non-zero when valid.  And, when a guest

arch/x86/kvm/mmu/paging.h

+5 −4
Original line number Diff line number Diff line
@@ -4,11 +4,12 @@ 
#define __KVM_X86_PAGING_H



#define GUEST_PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))



#define PT64_LVL_ADDR_MASK(level) \

	(GUEST_PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \

						* PT64_LEVEL_BITS))) - 1))

	__PT_LVL_ADDR_MASK(GUEST_PT64_BASE_ADDR_MASK, level, PT64_LEVEL_BITS)



#define PT64_LVL_OFFSET_MASK(level) \

	(GUEST_PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \

						* PT64_LEVEL_BITS))) - 1))

	__PT_LVL_OFFSET_MASK(GUEST_PT64_BASE_ADDR_MASK, level, PT64_LEVEL_BITS)



#endif /* __KVM_X86_PAGING_H */

arch/x86/kvm/mmu/spte.h

+3 −4
Original line number Diff line number Diff line
@@ -55,11 +55,10 @@ static_assert(SPTE_TDP_AD_ENABLED_MASK == 0); 


#define PT64_LEVEL_BITS 9



#define PT64_LEVEL_SHIFT(level) \

		(PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)

#define PT64_LEVEL_SHIFT(level) __PT_LEVEL_SHIFT(level, PT64_LEVEL_BITS)



#define PT64_INDEX(address, level) __PT_INDEX(address, level, PT64_LEVEL_BITS)



#define PT64_INDEX(address, level)\

	(((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))

#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)



/*