drm/i915/tc: switch to intel_de_* register accessors in display code (42bbdb81) · Commits · EulixOS / Software / Kernel

drivers/gpu/drm/i915/display/intel_tc.c

+18 −37

Original line number	Original line	Diff line number	Diff line
	@@ -5,6 +5,7 @@

	#include "i915_drv.h"		#include "i915_drv.h"
	#include "i915_reg.h"		#include "i915_reg.h"
			#include "intel_de.h"
	#include "intel_display.h"		#include "intel_display.h"
	#include "intel_display_power_map.h"		#include "intel_display_power_map.h"
	#include "intel_display_types.h"		#include "intel_display_types.h"
	@@ -120,11 +121,9 @@ assert_tc_cold_blocked(struct intel_digital_port *dig_port)
	u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)		u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
	{		{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);		struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	struct intel_uncore *uncore = &i915->uncore;
	u32 lane_mask;		u32 lane_mask;

	lane_mask = intel_uncore_read(uncore,		lane_mask = intel_de_read(i915, PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
	PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));

	drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff);		drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff);
	assert_tc_cold_blocked(dig_port);		assert_tc_cold_blocked(dig_port);
	@@ -136,11 +135,9 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
	u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)		u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
	{		{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);		struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	struct intel_uncore *uncore = &i915->uncore;
	u32 pin_mask;		u32 pin_mask;

	pin_mask = intel_uncore_read(uncore,		pin_mask = intel_de_read(i915, PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
	PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));

	drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff);		drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff);
	assert_tc_cold_blocked(dig_port);		assert_tc_cold_blocked(dig_port);
	@@ -186,7 +183,6 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
	{		{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);		struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;		bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
	struct intel_uncore *uncore = &i915->uncore;
	u32 val;		u32 val;

	drm_WARN_ON(&i915->drm,		drm_WARN_ON(&i915->drm,
	@@ -194,8 +190,7 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,

	assert_tc_cold_blocked(dig_port);		assert_tc_cold_blocked(dig_port);

	val = intel_uncore_read(uncore,		val = intel_de_read(i915, PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
	PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
	val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx);		val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx);

	switch (required_lanes) {		switch (required_lanes) {
	@@ -216,8 +211,7 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
	MISSING_CASE(required_lanes);		MISSING_CASE(required_lanes);
	}		}

	intel_uncore_write(uncore,		intel_de_write(i915, PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
	PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
	}		}

	static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,		static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
	@@ -246,13 +240,11 @@ static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
	static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)		static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
	{		{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);		struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	struct intel_uncore *uncore = &i915->uncore;
	u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];		u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
	u32 mask = 0;		u32 mask = 0;
	u32 val;		u32 val;

	val = intel_uncore_read(uncore,		val = intel_de_read(i915, PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
	PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));

	if (val == 0xffffffff) {		if (val == 0xffffffff) {
	drm_dbg_kms(&i915->drm,		drm_dbg_kms(&i915->drm,
	@@ -266,7 +258,7 @@ static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
	if (val & TC_LIVE_STATE_TC(dig_port->tc_phy_fia_idx))		if (val & TC_LIVE_STATE_TC(dig_port->tc_phy_fia_idx))
	mask \|= BIT(TC_PORT_DP_ALT);		mask \|= BIT(TC_PORT_DP_ALT);

	if (intel_uncore_read(uncore, SDEISR) & isr_bit)		if (intel_de_read(i915, SDEISR) & isr_bit)
	mask \|= BIT(TC_PORT_LEGACY);		mask \|= BIT(TC_PORT_LEGACY);

	/* The sink can be connected only in a single mode. */		/* The sink can be connected only in a single mode. */
	@@ -281,7 +273,6 @@ static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);		struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);		enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
	u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];		u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
	struct intel_uncore *uncore = &i915->uncore;
	u32 val, mask = 0;		u32 val, mask = 0;

	/*		/*
	@@ -289,13 +280,13 @@ static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
	* registers in IOM. Note that this doesn't apply to PHY and FIA		* registers in IOM. Note that this doesn't apply to PHY and FIA
	* registers.		* registers.
	*/		*/
	val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port));		val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
	if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT)		if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT)
	mask \|= BIT(TC_PORT_DP_ALT);		mask \|= BIT(TC_PORT_DP_ALT);
	if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT)		if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT)
	mask \|= BIT(TC_PORT_TBT_ALT);		mask \|= BIT(TC_PORT_TBT_ALT);

	if (intel_uncore_read(uncore, SDEISR) & isr_bit)		if (intel_de_read(i915, SDEISR) & isr_bit)
	mask \|= BIT(TC_PORT_LEGACY);		mask \|= BIT(TC_PORT_LEGACY);

	/* The sink can be connected only in a single mode. */		/* The sink can be connected only in a single mode. */
	@@ -326,11 +317,9 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
	static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)		static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
	{		{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);		struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	struct intel_uncore *uncore = &i915->uncore;
	u32 val;		u32 val;

	val = intel_uncore_read(uncore,		val = intel_de_read(i915, PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia));
	PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia));
	if (val == 0xffffffff) {		if (val == 0xffffffff) {
	drm_dbg_kms(&i915->drm,		drm_dbg_kms(&i915->drm,
	"Port %s: PHY in TCCOLD, assuming not complete\n",		"Port %s: PHY in TCCOLD, assuming not complete\n",
	@@ -352,10 +341,9 @@ static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port)
	{		{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);		struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);		enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
	struct intel_uncore *uncore = &i915->uncore;
	u32 val;		u32 val;

	val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port));		val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
	if (val == 0xffffffff) {		if (val == 0xffffffff) {
	drm_dbg_kms(&i915->drm,		drm_dbg_kms(&i915->drm,
	"Port %s: PHY in TCCOLD, assuming not complete\n",		"Port %s: PHY in TCCOLD, assuming not complete\n",
	@@ -380,11 +368,9 @@ static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
	bool take)		bool take)
	{		{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);		struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	struct intel_uncore *uncore = &i915->uncore;
	u32 val;		u32 val;

	val = intel_uncore_read(uncore,		val = intel_de_read(i915, PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
	PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
	if (val == 0xffffffff) {		if (val == 0xffffffff) {
	drm_dbg_kms(&i915->drm,		drm_dbg_kms(&i915->drm,
	"Port %s: PHY in TCCOLD, can't %s ownership\n",		"Port %s: PHY in TCCOLD, can't %s ownership\n",
	@@ -397,8 +383,7 @@ static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
	if (take)		if (take)
	val \|= DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);		val \|= DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);

	intel_uncore_write(uncore,		intel_de_write(i915, PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
	PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);

	return true;		return true;
	}		}
	@@ -407,10 +392,9 @@ static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
	bool take)		bool take)
	{		{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);		struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	struct intel_uncore *uncore = &i915->uncore;
	enum port port = dig_port->base.port;		enum port port = dig_port->base.port;

	intel_uncore_rmw(uncore, DDI_BUF_CTL(port), DDI_BUF_CTL_TC_PHY_OWNERSHIP,		intel_de_rmw(i915, DDI_BUF_CTL(port), DDI_BUF_CTL_TC_PHY_OWNERSHIP,
	take ? DDI_BUF_CTL_TC_PHY_OWNERSHIP : 0);		take ? DDI_BUF_CTL_TC_PHY_OWNERSHIP : 0);

	return true;		return true;
	@@ -429,11 +413,9 @@ static bool tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take
	static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port)		static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port)
	{		{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);		struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	struct intel_uncore *uncore = &i915->uncore;
	u32 val;		u32 val;

	val = intel_uncore_read(uncore,		val = intel_de_read(i915, PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
	PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
	if (val == 0xffffffff) {		if (val == 0xffffffff) {
	drm_dbg_kms(&i915->drm,		drm_dbg_kms(&i915->drm,
	"Port %s: PHY in TCCOLD, assume safe mode\n",		"Port %s: PHY in TCCOLD, assume safe mode\n",
	@@ -447,11 +429,10 @@ static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port)
	static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port)		static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port)
	{		{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);		struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	struct intel_uncore *uncore = &i915->uncore;
	enum port port = dig_port->base.port;		enum port port = dig_port->base.port;
	u32 val;		u32 val;

	val = intel_uncore_read(uncore, DDI_BUF_CTL(port));		val = intel_de_read(i915, DDI_BUF_CTL(port));
	return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP;		return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP;
	}		}

	@@ -907,7 +888,7 @@ tc_has_modular_fia(struct drm_i915_private i915, struct intel_digital_port dig

	mutex_lock(&dig_port->tc_lock);		mutex_lock(&dig_port->tc_lock);
	wakeref = tc_cold_block(dig_port, &domain);		wakeref = tc_cold_block(dig_port, &domain);
	val = intel_uncore_read(&i915->uncore, PORT_TX_DFLEXDPSP(FIA1));		val = intel_de_read(i915, PORT_TX_DFLEXDPSP(FIA1));
	tc_cold_unblock(dig_port, domain, wakeref);		tc_cold_unblock(dig_port, domain, wakeref);
	mutex_unlock(&dig_port->tc_lock);		mutex_unlock(&dig_port->tc_lock);