Commit 42b55972 authored by Peter Geis's avatar Peter Geis Committed by Vinod Koul
Browse files

phy: phy-rockchip-inno-usb2: add rk3568 support 



The rk3568 usb2phy is a standalone device with a single muxed interrupt.
Add support for the registers to the usb2phy driver.

Signed-off-by: default avatarPeter Geis <pgwipeout@gmail.com>
Tested-by: default avatarMichael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20211215210252.120923-7-pgwipeout@gmail.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent ed2b5a8e

drivers/phy/rockchip/phy-rockchip-inno-usb2.c

+65 −0
Original line number Diff line number Diff line
@@ -1092,6 +1092,7 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, 
	if (ret) {

		dev_err(rphy->dev, "failed to init irq for host port\n");

		goto out;

	}



	if (!IS_ERR(rphy->edev)) {

		rport->event_nb.notifier_call = rockchip_otg_event;
@@ -1503,6 +1504,69 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 
	{ /* sentinel */ }

};



static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {

	{

		.reg = 0xfe8a0000,

		.num_ports	= 2,

		.clkout_ctl	= { 0x0008, 4, 4, 1, 0 },

		.port_cfgs	= {

			[USB2PHY_PORT_OTG] = {

				.phy_sus	= { 0x0000, 8, 0, 0, 0x1d1 },

				.bvalid_det_en	= { 0x0080, 2, 2, 0, 1 },

				.bvalid_det_st	= { 0x0084, 2, 2, 0, 1 },

				.bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },

				.utmi_avalid	= { 0x00c0, 10, 10, 0, 1 },

				.utmi_bvalid	= { 0x00c0, 9, 9, 0, 1 },

			},

			[USB2PHY_PORT_HOST] = {

				/* Select suspend control from controller */

				.phy_sus	= { 0x0004, 8, 0, 0x1d2, 0x1d2 },

				.ls_det_en	= { 0x0080, 1, 1, 0, 1 },

				.ls_det_st	= { 0x0084, 1, 1, 0, 1 },

				.ls_det_clr	= { 0x0088, 1, 1, 0, 1 },

				.utmi_ls	= { 0x00c0, 17, 16, 0, 1 },

				.utmi_hstdet	= { 0x00c0, 19, 19, 0, 1 }

			}

		},

		.chg_det = {

			.opmode		= { 0x0000, 3, 0, 5, 1 },

			.cp_det		= { 0x00c0, 24, 24, 0, 1 },

			.dcp_det	= { 0x00c0, 23, 23, 0, 1 },

			.dp_det		= { 0x00c0, 25, 25, 0, 1 },

			.idm_sink_en	= { 0x0008, 8, 8, 0, 1 },

			.idp_sink_en	= { 0x0008, 7, 7, 0, 1 },

			.idp_src_en	= { 0x0008, 9, 9, 0, 1 },

			.rdm_pdwn_en	= { 0x0008, 10, 10, 0, 1 },

			.vdm_src_en	= { 0x0008, 12, 12, 0, 1 },

			.vdp_src_en	= { 0x0008, 11, 11, 0, 1 },

		},

	},

	{

		.reg = 0xfe8b0000,

		.num_ports	= 2,

		.clkout_ctl	= { 0x0008, 4, 4, 1, 0 },

		.port_cfgs	= {

			[USB2PHY_PORT_OTG] = {

				.phy_sus	= { 0x0000, 8, 0, 0x1d2, 0x1d1 },

				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },

				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },

				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },

				.utmi_ls	= { 0x00c0, 5, 4, 0, 1 },

				.utmi_hstdet	= { 0x00c0, 7, 7, 0, 1 }

			},

			[USB2PHY_PORT_HOST] = {

				.phy_sus	= { 0x0004, 8, 0, 0x1d2, 0x1d1 },

				.ls_det_en	= { 0x0080, 1, 1, 0, 1 },

				.ls_det_st	= { 0x0084, 1, 1, 0, 1 },

				.ls_det_clr	= { 0x0088, 1, 1, 0, 1 },

				.utmi_ls	= { 0x00c0, 17, 16, 0, 1 },

				.utmi_hstdet	= { 0x00c0, 19, 19, 0, 1 }

			}

		},

	},

	{ /* sentinel */ }

};



static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {

	{

		.reg = 0x100,
@@ -1552,6 +1616,7 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = { 
	{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },

	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },

	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },

	{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },

	{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },

	{}

};