Commit 429a64f6 authored by Athira Rajeev's avatar Athira Rajeev Committed by Michael Ellerman
Browse files

powerpc/perf: Only define power_pmu_wants_prompt_pmi() for CONFIG_PPC64 



power_pmu_wants_prompt_pmi() is used to decide if PMIs should be taken
promptly. This is valid only for ppc64 and is used only if
CONFIG_PPC_BOOK3S_64=y. Hence include the function under config check
for PPC64.

Fixes warning for 32-bit compilation:

  arch/powerpc/perf/core-book3s.c:2455:6: warning: no previous prototype for 'power_pmu_wants_prompt_pmi'
    2455 | bool power_pmu_wants_prompt_pmi(void)
         |      ^~~~~~~~~~~~~~~~~~~~~~~~~~

Fixes: 5a7745b9 ("powerpc/64s/perf: add power_pmu_wants_prompt_pmi to say whether perf wants PMIs to be soft-NMI")
Reported-by: default avatarkernel test robot <lkp@intel.com>
Signed-off-by: default avatarAthira Rajeev <atrajeev@linux.vnet.ibm.com>
Reviewed-by: default avatarNicholas Piggin <npiggin@gmail.com>
[mpe: Move inside existing CONFIG_PPC64 ifdef block]
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220114031355.87480-1-atrajeev@linux.vnet.ibm.com
parent d37823c3

arch/powerpc/perf/core-book3s.c

+28 −30
Original line number Diff line number Diff line
@@ -776,6 +776,34 @@ static void pmao_restore_workaround(bool ebb) 
	mtspr(SPRN_PMC6, pmcs[5]);

}



/*

 * If the perf subsystem wants performance monitor interrupts as soon as

 * possible (e.g., to sample the instruction address and stack chain),

 * this should return true. The IRQ masking code can then enable MSR[EE]

 * in some places (e.g., interrupt handlers) that allows PMI interrupts

 * through to improve accuracy of profiles, at the cost of some performance.

 *

 * The PMU counters can be enabled by other means (e.g., sysfs raw SPR

 * access), but in that case there is no need for prompt PMI handling.

 *

 * This currently returns true if any perf counter is being used. It

 * could possibly return false if only events are being counted rather than

 * samples being taken, but for now this is good enough.

 */

bool power_pmu_wants_prompt_pmi(void)

{

	struct cpu_hw_events *cpuhw;



	/*

	 * This could simply test local_paca->pmcregs_in_use if that were not

	 * under ifdef KVM.

	 */

	if (!ppmu)

		return false;



	cpuhw = this_cpu_ptr(&cpu_hw_events);

	return cpuhw->n_events;

}

#endif /* CONFIG_PPC64 */



static void perf_event_interrupt(struct pt_regs *regs);
@@ -2438,36 +2466,6 @@ static void perf_event_interrupt(struct pt_regs *regs) 
	perf_sample_event_took(sched_clock() - start_clock);

}



/*

 * If the perf subsystem wants performance monitor interrupts as soon as

 * possible (e.g., to sample the instruction address and stack chain),

 * this should return true. The IRQ masking code can then enable MSR[EE]

 * in some places (e.g., interrupt handlers) that allows PMI interrupts

 * though to improve accuracy of profiles, at the cost of some performance.

 *

 * The PMU counters can be enabled by other means (e.g., sysfs raw SPR

 * access), but in that case there is no need for prompt PMI handling.

 *

 * This currently returns true if any perf counter is being used. It

 * could possibly return false if only events are being counted rather than

 * samples being taken, but for now this is good enough.

 */

bool power_pmu_wants_prompt_pmi(void)

{

	struct cpu_hw_events *cpuhw;



	/*

	 * This could simply test local_paca->pmcregs_in_use if that were not

	 * under ifdef KVM.

	 */



	if (!ppmu)

		return false;



	cpuhw = this_cpu_ptr(&cpu_hw_events);

	return cpuhw->n_events;

}



static int power_pmu_prepare_cpu(unsigned int cpu)

{

	struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);