Commit 425e9e04 authored by Phil Edworthy's avatar Phil Edworthy Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a09g011: Add IIC clock and reset entries 



Add IIC groups clock and reset entries to CPG driver.
IIC Group A consists of IIC0 and IIC1. IIC Group B consists of
IIC2 and IIC3. To confuse things, IIC_PCLK0 is used by group A
and IIC_PCLK1 is used by group B.

Signed-off-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220819193944.337599-2-phil.edworthy@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 57746e99

drivers/clk/renesas/r9a09g011-cpg.c

+4 −0
Original line number Diff line number Diff line
@@ -132,6 +132,8 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { 
	DEF_COUPLED("eth_chi",	R9A09G011_ETH0_CLK_CHI,	 CLK_PLL2_100, 0x40c, 8),

	DEF_MOD("eth_clk_gptp",	R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),

	DEF_MOD("syc_cnt_clk",	R9A09G011_SYC_CNT_CLK,	 CLK_MAIN_24,  0x41c, 12),

	DEF_MOD("iic_pclk0",	R9A09G011_IIC_PCLK0,	 CLK_SEL_E,    0x420, 12),

	DEF_MOD("iic_pclk1",	R9A09G011_IIC_PCLK1,	 CLK_SEL_E,    0x424, 12),

	DEF_MOD("wdt0_pclk",	R9A09G011_WDT0_PCLK,	 CLK_SEL_E,    0x428, 12),

	DEF_MOD("wdt0_clk",	R9A09G011_WDT0_CLK,	 CLK_MAIN,     0x428, 13),

	DEF_MOD("urt_pclk",	R9A09G011_URT_PCLK,	 CLK_SEL_E,    0x438, 4),
@@ -143,6 +145,8 @@ static const struct rzg2l_reset r9a09g011_resets[] = { 
	DEF_RST(R9A09G011_PFC_PRESETN,		0x600, 2),

	DEF_RST_MON(R9A09G011_ETH0_RST_HW_N,	0x608, 11, 11),

	DEF_RST_MON(R9A09G011_SYC_RST_N,	0x610, 9,  13),

	DEF_RST(R9A09G011_IIC_GPA_PRESETN,	0x614, 8),

	DEF_RST(R9A09G011_IIC_GPB_PRESETN,	0x614, 9),

	DEF_RST_MON(R9A09G011_WDT0_PRESETN,	0x614, 12, 19),

};