Commit 425ad8a5 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/pm: use adverse selection for dpm features unsupported by driver 



It's vbios and pmfw instead of driver who decide whether some dpm features
is supported or not. Driver just de-selects those features which are not
permitted on user's request. Thus, we use adverse selects model.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ce754eb9

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

+24 −61
Original line number Diff line number Diff line
@@ -244,79 +244,42 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, 
	if (num > 2)

		return -EINVAL;



	memset(feature_mask, 0, sizeof(uint32_t) * num);

	memset(feature_mask, 0xff, sizeof(uint32_t) * num);



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT);



	if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);

	if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) {

		*(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);

		*(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT);

	}



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT);

	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT);



	if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) &&

	    (adev->pg_flags & AMD_PG_SUPPORT_MMHUB))

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);

	if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) ||

	    !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB))

		*(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);



	if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);

	if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK))

		*(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);



	/* PMFW 78.58 contains a critical fix for gfxoff feature */

	smu_cmn_get_smc_version(smu, NULL, &smu_version);

	if ((smu_version >= 0x004e3a00) &&

	    (adev->pm.pp_feature & PP_GFXOFF_MASK))

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT);

	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT);



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT);

	if ((smu_version < 0x004e3a00) ||

	     !(adev->pm.pp_feature & PP_GFXOFF_MASK))

		*(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT);



	if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);

	if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {

		*(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT);

		*(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);

		*(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);

	}



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT);

	if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK))

		*(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);



	if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);

	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);

	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT);

	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT);

	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT);

	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_DCFCLK_BIT);



	if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) {

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);

	if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {

		*(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT);

		*(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT);

	}



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT);



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT);

	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT);



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);

	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT);



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT);



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT);



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_UCLK_BIT);



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT);



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);



	if (adev->pm.pp_feature & PP_ULV_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);

	if (!(adev->pm.pp_feature & PP_ULV_MASK))

		*(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT);



	return 0;

}