Commit 422ec6fe authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge tag 'opp-updates-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm 

Pull OPP updates for 6.6 from Viresh Kumar:

"- Minor core cleanup and addition of new frequency related APIs (Viresh
   Kumar and Manivannan Sadhasivam).

 - Convert ti cpufreq/opp bindings to json schema (Nishanth Menon)."

* tag 'opp-updates-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm:
  dt-bindings: cpufreq: Convert ti-cpufreq to json schema
  dt-bindings: opp: Convert ti-omap5-opp-supply to json schema
  OPP: Fix argument name in doc comment
  dt-bindings: opp: Increase maxItems for opp-hz property
  OPP: Fix passing 0 to PTR_ERR in _opp_attach_genpd()
  OPP: Fix potential null ptr dereference in dev_pm_opp_get_required_pstate()
  OPP: Reuse dev_pm_opp_get_freq_indexed()
  OPP: Update _read_freq() to return the correct frequency
  OPP: Add dev_pm_opp_find_freq_exact_indexed()
  OPP: Introduce dev_pm_opp_get_freq_indexed() API
  OPP: Introduce dev_pm_opp_find_freq_{ceil/floor}_indexed() APIs
  OPP: Rearrange entries in pm_opp.h
parents 2114d596 e576a9a8

Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt

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TI CPUFreq and OPP bindings

================================



Certain TI SoCs, like those in the am335x, am437x, am57xx, and dra7xx

families support different OPPs depending on the silicon variant in use.

The ti-cpufreq driver can use revision and an efuse value from the SoC to

provide the OPP framework with supported hardware information. This is

used to determine which OPPs from the operating-points-v2 table get enabled

when it is parsed by the OPP framework.



Required properties:

--------------------

In 'cpus' nodes:

- operating-points-v2: Phandle to the operating-points-v2 table to use.



In 'operating-points-v2' table:

- compatible: Should be

	- 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx,

	  omap34xx, omap36xx and am3517 SoCs

- syscon: A phandle pointing to a syscon node representing the control module

	  register space of the SoC.



Optional properties:

--------------------

- "vdd-supply", "vbb-supply": to define two regulators for dra7xx

- "cpu0-supply", "vbb-supply": to define two regulators for omap36xx



For each opp entry in 'operating-points-v2' table:

- opp-supported-hw: Two bitfields indicating:

	1. Which revision of the SoC the OPP is supported by

	2. Which eFuse bits indicate this OPP is available



	A bitwise AND is performed against these values and if any bit

	matches, the OPP gets enabled.



Example:

--------



/* From arch/arm/boot/dts/am33xx.dtsi */

cpus {

	#address-cells = <1>;

	#size-cells = <0>;

	cpu@0 {

		compatible = "arm,cortex-a8";

		device_type = "cpu";

		reg = <0>;



		operating-points-v2 = <&cpu0_opp_table>;



		clocks = <&dpll_mpu_ck>;

		clock-names = "cpu";



		clock-latency = <300000>; /* From omap-cpufreq driver */

	};

};



/*

 * cpu0 has different OPPs depending on SoC revision and some on revisions

 * 0x2 and 0x4 have eFuse bits that indicate if they are available or not

 */

cpu0_opp_table: opp-table {

	compatible = "operating-points-v2-ti-cpu";

	syscon = <&scm_conf>;



	/*

	 * The three following nodes are marked with opp-suspend

	 * because they can not be enabled simultaneously on a

	 * single SoC.

	 */

	opp50-300000000 {

		opp-hz = /bits/ 64 <300000000>;

		opp-microvolt = <950000 931000 969000>;

		opp-supported-hw = <0x06 0x0010>;

		opp-suspend;

	};



	opp100-275000000 {

		opp-hz = /bits/ 64 <275000000>;

		opp-microvolt = <1100000 1078000 1122000>;

		opp-supported-hw = <0x01 0x00FF>;

		opp-suspend;

	};



	opp100-300000000 {

		opp-hz = /bits/ 64 <300000000>;

		opp-microvolt = <1100000 1078000 1122000>;

		opp-supported-hw = <0x06 0x0020>;

		opp-suspend;

	};



	opp100-500000000 {

		opp-hz = /bits/ 64 <500000000>;

		opp-microvolt = <1100000 1078000 1122000>;

		opp-supported-hw = <0x01 0xFFFF>;

	};



	opp100-600000000 {

		opp-hz = /bits/ 64 <600000000>;

		opp-microvolt = <1100000 1078000 1122000>;

		opp-supported-hw = <0x06 0x0040>;

	};



	opp120-600000000 {

		opp-hz = /bits/ 64 <600000000>;

		opp-microvolt = <1200000 1176000 1224000>;

		opp-supported-hw = <0x01 0xFFFF>;

	};



	opp120-720000000 {

		opp-hz = /bits/ 64 <720000000>;

		opp-microvolt = <1200000 1176000 1224000>;

		opp-supported-hw = <0x06 0x0080>;

	};



	oppturbo-720000000 {

		opp-hz = /bits/ 64 <720000000>;

		opp-microvolt = <1260000 1234800 1285200>;

		opp-supported-hw = <0x01 0xFFFF>;

	};



	oppturbo-800000000 {

		opp-hz = /bits/ 64 <800000000>;

		opp-microvolt = <1260000 1234800 1285200>;

		opp-supported-hw = <0x06 0x0100>;

	};



	oppnitro-1000000000 {

		opp-hz = /bits/ 64 <1000000000>;

		opp-microvolt = <1325000 1298500 1351500>;

		opp-supported-hw = <0x04 0x0200>;

	};

};

Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/opp/operating-points-v2-ti-cpu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: TI CPU OPP (Operating Performance Points)



description:

  TI SoCs, like those in the AM335x, AM437x, AM57xx, AM62x, and DRA7xx

  families, the CPU frequencies subset and the voltage value of each

  OPP vary based on the silicon variant used. The data sheet sections

  corresponding to "Operating Performance Points" describe the frequency

  and voltage values based on device type and speed bin information

  blown in corresponding eFuse bits as referred to by the Technical

  Reference Manual.



  This document extends the operating-points-v2 binding by providing

  the hardware description for the scheme mentioned above.



maintainers:

  - Nishanth Menon <nm@ti.com>



allOf:

  - $ref: opp-v2-base.yaml#



properties:

  compatible:

    const: operating-points-v2-ti-cpu



  syscon:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: |

      points to syscon node representing the control module

      register space of the SoC.



  opp-shared: true



patternProperties:

  '^opp(-?[0-9]+)*$':

    type: object

    additionalProperties: false



    properties:

      clock-latency-ns: true

      opp-hz: true

      opp-microvolt: true

      opp-supported-hw: true

      opp-suspend: true

      turbo-mode: true



    required:

      - opp-hz

      - opp-supported-hw



required:

  - compatible

  - syscon



additionalProperties: false



examples:

  - |

    opp-table {

        compatible = "operating-points-v2-ti-cpu";

        syscon = <&scm_conf>;



        opp-300000000 {

            opp-hz = /bits/ 64 <300000000>;

            opp-microvolt = <1100000 1078000 1122000>;

            opp-supported-hw = <0x06 0x0020>;

            opp-suspend;

        };



        opp-500000000 {

            opp-hz = /bits/ 64 <500000000>;

            opp-microvolt = <1100000 1078000 1122000>;

            opp-supported-hw = <0x01 0xFFFF>;

        };



        opp-600000000 {

            opp-hz = /bits/ 64 <600000000>;

            opp-microvolt = <1100000 1078000 1122000>;

            opp-supported-hw = <0x06 0x0040>;

        };



        opp-1000000000 {

            opp-hz = /bits/ 64 <1000000000>;

            opp-microvolt = <1325000 1298500 1351500>;

            opp-supported-hw = <0x04 0x0200>;

        };

    };

Documentation/devicetree/bindings/opp/opp-v2-base.yaml

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@@ -56,7 +56,7 @@ patternProperties: 
          need to be configured and that is left for the implementation

          specific binding.

        minItems: 1

        maxItems: 16

        maxItems: 32

        items:

          maxItems: 1

Documentation/devicetree/bindings/opp/ti,omap-opp-supply.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/opp/ti,omap-opp-supply.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Texas Instruments OMAP compatible OPP supply



description:

  OMAP5, DRA7, and AM57 families of SoCs have Class 0 AVS eFuse

  registers, which contain OPP-specific voltage information tailored

  for the specific device. This binding provides the information

  needed to describe such a hardware values and relate them to program

  the primary regulator during an OPP transition.



  Also, some supplies may have an associated vbb-supply, an Adaptive

  Body Bias regulator, which must transition in a specific sequence

  w.r.t the vdd-supply and clk when making an OPP transition. By

  supplying two regulators to the device that will undergo OPP

  transitions, we can use the multi-regulator support implemented by

  the OPP core to describe both regulators the platform needs. The

  OPP core binding Documentation/devicetree/bindings/opp/opp-v2.yaml

  provides further information (refer to Example 4 Handling multiple

  regulators).



maintainers:

  - Nishanth Menon <nm@ti.com>



properties:

  $nodename:

    pattern: '^opp-supply(@[0-9a-f]+)?$'



  compatible:

    oneOf:

      - description: Basic OPP supply controlling VDD and VBB

        const: ti,omap-opp-supply

      - description: OMAP5+ optimized voltages in efuse(Class 0) VDD along with

          VBB.

        const: ti,omap5-opp-supply

      - description: OMAP5+ optimized voltages in efuse(class0) VDD but no VBB

        const: ti,omap5-core-opp-supply



  reg:

    maxItems: 1



  ti,absolute-max-voltage-uv:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: Absolute maximum voltage for the OPP supply in micro-volts.

    minimum: 750000

    maximum: 1500000



  ti,efuse-settings:

    description: An array of u32 tuple items providing information about

      optimized efuse configuration.

    minItems: 1

    $ref: /schemas/types.yaml#/definitions/uint32-matrix

    items:

      items:

        - description: Reference voltage in micro-volts (OPP Voltage)

          minimum: 750000

          maximum: 1500000

          multipleOf: 10000

        - description: efuse offset where the optimized voltage is located

          multipleOf: 4

          maximum: 256



required:

  - compatible

  - ti,absolute-max-voltage-uv



allOf:

  - if:

      not:

        properties:

          compatible:

            contains:

              const: ti,omap-opp-supply

    then:

      required:

        - reg

        - ti,efuse-settings



additionalProperties: false



examples:

  - |

    opp-supply {

        compatible = "ti,omap-opp-supply";

        ti,absolute-max-voltage-uv = <1375000>;

    };

  - |

    opp-supply@4a003b20 {

        compatible = "ti,omap5-opp-supply";

        reg = <0x4a003b20 0x8>;

        ti,efuse-settings =

            /* uV   offset */

            <1060000 0x0>,

            <1160000 0x4>,

            <1210000 0x8>;

        ti,absolute-max-voltage-uv = <1500000>;

    };

Documentation/devicetree/bindings/opp/ti-omap5-opp-supply.txt

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Texas Instruments OMAP compatible OPP supply description



OMAP5, DRA7, and AM57 family of SoCs have Class0 AVS eFuse registers which

contain data that can be used to adjust voltages programmed for some of their

supplies for more efficient operation. This binding provides the information

needed to read these values and use them to program the main regulator during

an OPP transitions.



Also, some supplies may have an associated vbb-supply which is an Adaptive Body

Bias regulator which much be transitioned in a specific sequence with regards

to the vdd-supply and clk when making an OPP transition. By supplying two

regulators to the device that will undergo OPP transitions we can make use

of the multi regulator binding that is part of the OPP core described here [1]

to describe both regulators needed by the platform.



[1] Documentation/devicetree/bindings/opp/opp-v2.yaml



Required Properties for Device Node:

- vdd-supply: phandle to regulator controlling VDD supply

- vbb-supply: phandle to regulator controlling Body Bias supply

	      (Usually Adaptive Body Bias regulator)



Required Properties for opp-supply node:

- compatible: Should be one of:

	"ti,omap-opp-supply" - basic OPP supply controlling VDD and VBB

	"ti,omap5-opp-supply" - OMAP5+ optimized voltages in efuse(class0)VDD

			    along with VBB

	"ti,omap5-core-opp-supply" - OMAP5+ optimized voltages in efuse(class0) VDD

			    but no VBB.

- reg: Address and length of the efuse register set for the device (mandatory

	only for "ti,omap5-opp-supply")

- ti,efuse-settings: An array of u32 tuple items providing information about

	optimized efuse configuration. Each item consists of the following:

	volt: voltage in uV - reference voltage (OPP voltage)

	efuse_offseet: efuse offset from reg where the optimized voltage is stored.

- ti,absolute-max-voltage-uv: absolute maximum voltage for the OPP supply.



Example:



/* Device Node (CPU)  */

cpus {

	cpu0: cpu@0 {

		device_type = "cpu";



		...



		vdd-supply = <&vcc>;

		vbb-supply = <&abb_mpu>;

	};

};



/* OMAP OPP Supply with Class0 registers */

opp_supply_mpu: opp_supply@4a003b20 {

	compatible = "ti,omap5-opp-supply";

	reg = <0x4a003b20 0x8>;

	ti,efuse-settings = <

	/* uV   offset */

	1060000 0x0

	1160000 0x4

	1210000 0x8

	>;

	ti,absolute-max-voltage-uv = <1500000>;

};