Commit 42296edb authored by Luca Weiss's avatar Luca Weiss Committed by Yifan Qiao
Browse files

clk: qcom: dispcc-sm6350: Add missing parent_map for a clock 

mainline inclusion
from mainline-v6.14-rc1
commit d4cdb196f182d2fbe336c968228be00d8c3fed05
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IBRED1
CVE: CVE-2024-58080

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d4cdb196f182d2fbe336c968228be00d8c3fed05



--------------------------------

If a clk_rcg2 has a parent, it should also have parent_map defined,
otherwise we'll get a NULL pointer dereference when calling clk_set_rate
like the following:

  [    3.388105] Call trace:
  [    3.390664]  qcom_find_src_index+0x3c/0x70 (P)
  [    3.395301]  qcom_find_src_index+0x1c/0x70 (L)
  [    3.399934]  _freq_tbl_determine_rate+0x48/0x100
  [    3.404753]  clk_rcg2_determine_rate+0x1c/0x28
  [    3.409387]  clk_core_determine_round_nolock+0x58/0xe4
  [    3.421414]  clk_core_round_rate_nolock+0x48/0xfc
  [    3.432974]  clk_core_round_rate_nolock+0xd0/0xfc
  [    3.444483]  clk_core_set_rate_nolock+0x8c/0x300
  [    3.455886]  clk_set_rate+0x38/0x14c

Add the parent_map property for the clock where it's missing and also
un-inline the parent_data as well to keep the matching parent_map and
parent_data together.

Fixes: 83751977 ("clk: qcom: Add display clock controller driver for SM6350")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarLuca Weiss <luca.weiss@fairphone.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241220-sm6350-parent_map-v1-2-64f3d04cb2eb@fairphone.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Signed-off-by: default avatarYifan Qiao <qiaoyifan4@huawei.com>
parent 9d22d5b7

drivers/clk/qcom/dispcc-sm6350.c

+3 −4
Original line number Diff line number Diff line
@@ -187,13 +187,12 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { 
	.cmd_rcgr = 0x1144,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = disp_cc_parent_map_6,

	.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_dp_aux_clk_src",

		.parent_data = &(const struct clk_parent_data){

			.fw_name = "bi_tcxo",

		},

		.num_parents = 1,

		.parent_data = disp_cc_parent_data_6,

		.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),

		.ops = &clk_rcg2_ops,

	},

};