Commit 4215a119 authored by Horace Chen's avatar Horace Chen Committed by Alex Deucher
Browse files

drm/amdgpu: enable one vf mode on sienna cichlid vf 



sienna cichlid needs one vf mode which allows vf to set and get
clock status from guest vm. So now expose the required interface
and allow some smu request on VF mode. Also since this asic blocked
direct MMIO access, use KIQ to send SMU request under sriov vf.

OD use same command as getting pp table which is not allowed for
 sienna cichlid, so remove OD feature under sriov vf.

Signed-off-by: default avatarHorace Chen <horace.chen@amd.com>
Reviewed-by: default avatarMonk <Liu&lt;monk.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 152bb95c

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+2 −0
Original line number Diff line number Diff line
@@ -2045,6 +2045,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) 
	adev->pm.pp_feature = amdgpu_pp_feature_mask;

	if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)

		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;

	if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)

		adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;



	for (i = 0; i < adev->num_ip_blocks; i++) {

		if ((amdgpu_ip_block_mask & (1 << i)) == 0) {

drivers/gpu/drm/amd/pm/amdgpu_pm.c

+1 −1
Original line number Diff line number Diff line
@@ -1750,7 +1750,7 @@ static ssize_t amdgpu_get_gpu_metrics(struct device *dev, 


static struct amdgpu_device_attr amdgpu_device_attrs[] = {

	AMDGPU_DEVICE_ATTR_RW(power_dpm_state,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),

	AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,	ATTR_FLAG_BASIC),

	AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,	ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),

	AMDGPU_DEVICE_ATTR_RO(pp_num_states,				ATTR_FLAG_BASIC),

	AMDGPU_DEVICE_ATTR_RO(pp_cur_state,				ATTR_FLAG_BASIC),

	AMDGPU_DEVICE_ATTR_RW(pp_force_state,				ATTR_FLAG_BASIC),

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

+6 −4
Original line number Diff line number Diff line
@@ -653,11 +653,13 @@ static int smu_late_init(void *handle) 
		return ret;

	}



	if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {

		ret = smu_set_default_od_settings(smu);

		if (ret) {

			dev_err(adev->dev, "Failed to setup default OD settings!\n");

			return ret;

		}

	}



	ret = smu_populate_umd_state_clk(smu);

	if (ret) {

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+5 −5
Original line number Diff line number Diff line
@@ -89,17 +89,17 @@ static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] 
	MSG_MAP(GetEnabledSmuFeaturesHigh,	PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),

	MSG_MAP(SetWorkloadMask,		PPSMC_MSG_SetWorkloadMask,             1),

	MSG_MAP(SetPptLimit,			PPSMC_MSG_SetPptLimit,                 0),

	MSG_MAP(SetDriverDramAddrHigh,		PPSMC_MSG_SetDriverDramAddrHigh,       0),

	MSG_MAP(SetDriverDramAddrLow,		PPSMC_MSG_SetDriverDramAddrLow,        0),

	MSG_MAP(SetDriverDramAddrHigh,		PPSMC_MSG_SetDriverDramAddrHigh,       1),

	MSG_MAP(SetDriverDramAddrLow,		PPSMC_MSG_SetDriverDramAddrLow,        1),

	MSG_MAP(SetToolsDramAddrHigh,		PPSMC_MSG_SetToolsDramAddrHigh,        0),

	MSG_MAP(SetToolsDramAddrLow,		PPSMC_MSG_SetToolsDramAddrLow,         0),

	MSG_MAP(TransferTableSmu2Dram,		PPSMC_MSG_TransferTableSmu2Dram,       0),

	MSG_MAP(TransferTableSmu2Dram,		PPSMC_MSG_TransferTableSmu2Dram,       1),

	MSG_MAP(TransferTableDram2Smu,		PPSMC_MSG_TransferTableDram2Smu,       0),

	MSG_MAP(UseDefaultPPTable,		PPSMC_MSG_UseDefaultPPTable,           0),

	MSG_MAP(RunDcBtc,			PPSMC_MSG_RunDcBtc,                    0),

	MSG_MAP(EnterBaco,			PPSMC_MSG_EnterBaco,                   0),

	MSG_MAP(SetSoftMinByFreq,		PPSMC_MSG_SetSoftMinByFreq,            0),

	MSG_MAP(SetSoftMaxByFreq,		PPSMC_MSG_SetSoftMaxByFreq,            0),

	MSG_MAP(SetSoftMinByFreq,		PPSMC_MSG_SetSoftMinByFreq,            1),

	MSG_MAP(SetSoftMaxByFreq,		PPSMC_MSG_SetSoftMaxByFreq,            1),

	MSG_MAP(SetHardMinByFreq,		PPSMC_MSG_SetHardMinByFreq,            1),

	MSG_MAP(SetHardMaxByFreq,		PPSMC_MSG_SetHardMaxByFreq,            0),

	MSG_MAP(GetMinDpmFreq,			PPSMC_MSG_GetMinDpmFreq,               1),

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

+6 −6
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ static void smu_cmn_read_arg(struct smu_context *smu, 
{

	struct amdgpu_device *adev = smu->adev;



	*arg = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82);

	*arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);

}



static int smu_cmn_wait_for_response(struct smu_context *smu)
@@ -82,7 +82,7 @@ static int smu_cmn_wait_for_response(struct smu_context *smu) 
	uint32_t cur_value, i, timeout = adev->usec_timeout * 10;



	for (i = 0; i < timeout; i++) {

		cur_value = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90);

		cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);

		if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)

			return cur_value;
@@ -93,7 +93,7 @@ static int smu_cmn_wait_for_response(struct smu_context *smu) 
	if (i == timeout)

		return -ETIME;



	return RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90);

	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);

}



int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
@@ -111,9 +111,9 @@ int smu_cmn_send_msg_without_waiting(struct smu_context *smu, 
		return ret;

	}



	WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);

	WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82, param);

	WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);

	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);

	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);

	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);



	return 0;

}