Unverified Commit 41dd63cc authored by Ranjani Sridharan's avatar Ranjani Sridharan Committed by Mark Brown
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ASoC: SOF: Intel: TGL: set core_get/put ops 



Set core_get/put() ops for TGL. When core_get()
is requested for a core, its ref_count is incremented
and the PM_CORE_ENABLE IPC sent to the firmware to
power up the core if the current ref_count is 1.
Conversely, the ref_count is decremented in core_put()
and an IPC is sent to the DSP to power off the core
if the ref_count is 0.

Signed-off-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: default avatarGuennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: default avatarKai Vehmanen <kai.vehmanen@linux.intel.com>
Link: https://lore.kernel.org/r/20211119192621.4096077-5-kai.vehmanen@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent c414d5df

sound/soc/sof/intel/tgl.c

+42 −0
Original line number Diff line number Diff line
@@ -20,6 +20,46 @@ static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { 
	{"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},

};



static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core)

{

	struct sof_ipc_pm_core_config pm_core_config = {

		.hdr = {

			.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE,

			.size = sizeof(pm_core_config),

		},

		.enable_mask = sdev->enabled_cores_mask | BIT(core),

	};



	/* power up primary core if not already powered up and return */

	if (core == SOF_DSP_PRIMARY_CORE)

		return hda_dsp_enable_core(sdev, BIT(core));



	/* notify DSP for secondary cores */

	return sof_ipc_tx_message(sdev->ipc, pm_core_config.hdr.cmd,

				 &pm_core_config, sizeof(pm_core_config),

				 &pm_core_config, sizeof(pm_core_config));

}



static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)

{

	struct sof_ipc_pm_core_config pm_core_config = {

		.hdr = {

			.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE,

			.size = sizeof(pm_core_config),

		},

		.enable_mask = sdev->enabled_cores_mask & ~BIT(core),

	};



	/* power down primary core and return */

	if (core == SOF_DSP_PRIMARY_CORE)

		return hda_dsp_core_reset_power_down(sdev, BIT(core));



	/* notify DSP for secondary cores */

	return sof_ipc_tx_message(sdev->ipc, pm_core_config.hdr.cmd,

				 &pm_core_config, sizeof(pm_core_config),

				 &pm_core_config, sizeof(pm_core_config));

}



/* Tigerlake ops */

const struct snd_sof_dsp_ops sof_tgl_ops = {

	/* probe/remove/shutdown */
@@ -96,6 +136,8 @@ const struct snd_sof_dsp_ops sof_tgl_ops = { 
	/* dsp core power up/down */

	.core_power_up = hda_dsp_enable_core,

	.core_power_down = hda_dsp_core_reset_power_down,

	.core_get = tgl_dsp_core_get,

	.core_put = tgl_dsp_core_put,



	/* firmware run */

	.run = hda_dsp_cl_boot_firmware_iccmax,