Loading arch/arm/boot/dts/imx6q.dtsi +17 −0 Original line number Diff line number Diff line Loading @@ -338,3 +338,20 @@ }; }; }; &ldb { clocks = <&clks 33>, <&clks 34>, <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>, <&clks 135>, <&clks 136>; clock-names = "di0_pll", "di1_pll", "di0_sel", "di1_sel", "di2_sel", "di3_sel", "di0", "di1"; lvds-channel@0 { crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; }; lvds-channel@1 { crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; }; }; arch/arm/boot/dts/imx6qdl.dtsi +20 −0 Original line number Diff line number Diff line Loading @@ -536,6 +536,26 @@ reg = <0x020e0000 0x38>; }; ldb: ldb@020e0008 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; gpr = <&gpr>; status = "disabled"; lvds-channel@0 { reg = <0>; crtcs = <&ipu1 0>; status = "disabled"; }; lvds-channel@1 { reg = <1>; crtcs = <&ipu1 1>; status = "disabled"; }; }; dcic1: dcic@020e4000 { reg = <0x020e4000 0x4000>; interrupts = <0 124 0x04>; Loading Loading
arch/arm/boot/dts/imx6q.dtsi +17 −0 Original line number Diff line number Diff line Loading @@ -338,3 +338,20 @@ }; }; }; &ldb { clocks = <&clks 33>, <&clks 34>, <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>, <&clks 135>, <&clks 136>; clock-names = "di0_pll", "di1_pll", "di0_sel", "di1_sel", "di2_sel", "di3_sel", "di0", "di1"; lvds-channel@0 { crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; }; lvds-channel@1 { crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; }; };
arch/arm/boot/dts/imx6qdl.dtsi +20 −0 Original line number Diff line number Diff line Loading @@ -536,6 +536,26 @@ reg = <0x020e0000 0x38>; }; ldb: ldb@020e0008 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; gpr = <&gpr>; status = "disabled"; lvds-channel@0 { reg = <0>; crtcs = <&ipu1 0>; status = "disabled"; }; lvds-channel@1 { reg = <1>; crtcs = <&ipu1 1>; status = "disabled"; }; }; dcic1: dcic@020e4000 { reg = <0x020e4000 0x4000>; interrupts = <0 124 0x04>; Loading