Commit 41badc01 authored by Gustavo Sousa's avatar Gustavo Sousa Committed by Matt Roper
Browse files

drm/i915/gt: Convert PSS_MODE2 to multicast register 



That register became a multicast register as of Xe_HP and it is
currently used only for DG2. Use a proper prefix since there could be
usage of the same register for previous platforms in the future, which
would require a different definition (i.e. using _MMIO).

Note that, in its current state, the code does not cause functional
problems, since the actual application of the workaround would
implicitly use multicast mode. This fix is more toward consistency and
being future-proof uses of this register outside of workarounds.

v2:
  - Add paragraph noting that this change is for consistency and
    making the code future-proof. (Matt)

Signed-off-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Matthew Atwood <matthew.s.atwood@intel.com>
Fixes: 468a4e63 ("drm/i915/dg2: Introduce Wa_18018764978")
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230120181423.90507-1-gustavo.sousa@intel.com
parent 8d7eb8ed

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -464,7 +464,7 @@ 
#define GEN8_L3CNTLREG				_MMIO(0x7034)

#define   GEN8_ERRDETBCTRL			(1 << 9)



#define PSS_MODE2				_MMIO(0x703c)

#define XEHP_PSS_MODE2				MCR_REG(0x703c)

#define   SCOREBOARD_STALL_FLUSH_CONTROL	REG_BIT(5)



#define GEN7_SC_INSTDONE			_MMIO(0x7100)

drivers/gpu/drm/i915/gt/intel_workarounds.c

+2 −2
Original line number Diff line number Diff line
@@ -793,7 +793,7 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 
	/* Wa_18018764978:dg2 */

	if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) ||

	    IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))

		wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);

		wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);



	/* Wa_15010599737:dg2 */

	wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
@@ -821,7 +821,7 @@ static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine, 
		wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS);



		/* Wa_18018764978 */

		wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);

		wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);

	}



	/* Wa_18019271663 */