Commit 41a1f096 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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clk: tegra20/30: Explicitly set parent clock for Video Decoder 



The VDE parent won't be changed automatically to PLLC if bootloader
didn't do that for us, hence let's explicitly set the parent for
consistency.

Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent cb98598e

drivers/clk/tegra/clk-tegra20.c

+1 −1
Original line number Diff line number Diff line
@@ -1048,7 +1048,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { 
	{ TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 },

	{ TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },

	{ TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },

	{ TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 },

	{ TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 },

	/* must be the last entry */

	{ TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },

};

drivers/clk/tegra/clk-tegra30.c

+1 −1
Original line number Diff line number Diff line
@@ -1256,7 +1256,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { 
	{ TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },

	{ TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },

	{ TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 },

	{ TEGRA30_CLK_VDE, TEGRA30_CLK_CLK_MAX, 600000000, 0 },

	{ TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 600000000, 0 },

	{ TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },

	{ TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },

	{ TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },