Commit 41724ea2 authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Lyude Paul
Browse files

drm/amd/display: Add DP 2.0 MST DM Support 



[Why]
Add DP2 MST and debugfs support

[How]
Update the slot info based on the link encoding format

Reviewed-by: default avatar"Lin, Wayne" <Wayne.Lin@amd.com>
Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarFangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: default avatarLyude Paul <lyude@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211025223825.301703-5-lyude@redhat.com
parent d740e0bf

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+29 −0
Original line number Diff line number Diff line
@@ -10684,6 +10684,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, 
#if defined(CONFIG_DRM_AMD_DC_DCN)

	struct dsc_mst_fairness_vars vars[MAX_PIPES];

#endif

	struct drm_dp_mst_topology_state *mst_state;

	struct drm_dp_mst_topology_mgr *mgr;



	trace_amdgpu_dm_atomic_check_begin(state);
@@ -10891,6 +10893,33 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, 
		lock_and_validation_needed = true;

	}



#if defined(CONFIG_DRM_AMD_DC_DCN)

	/* set the slot info for each mst_state based on the link encoding format */

	for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {

		struct amdgpu_dm_connector *aconnector;

		struct drm_connector *connector;

		struct drm_connector_list_iter iter;

		u8 link_coding_cap;



		if (!mgr->mst_state )

			continue;



		drm_connector_list_iter_begin(dev, &iter);

		drm_for_each_connector_iter(connector, &iter) {

			int id = connector->index;



			if (id == mst_state->mgr->conn_base_id) {

				aconnector = to_amdgpu_dm_connector(connector);

				link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);

				drm_dp_mst_update_slots(mst_state, link_coding_cap);



				break;

			}

		}

		drm_connector_list_iter_end(&iter);



	}

#endif

	/**

	 * Streams and planes are reset when there are changes that affect

	 * bandwidth. Anything that affects bandwidth needs to go through

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

+3 −0
Original line number Diff line number Diff line
@@ -294,6 +294,9 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 
	case LINK_RATE_RBR2:

	case LINK_RATE_HIGH2:

	case LINK_RATE_HIGH3:

#if defined(CONFIG_DRM_AMD_DC_DCN)

	case LINK_RATE_UHBR10:

#endif

		break;

	default:

		valid_input = false;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

+4 −1
Original line number Diff line number Diff line
@@ -219,6 +219,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( 
	struct drm_dp_mst_topology_mgr *mst_mgr;

	struct drm_dp_mst_port *mst_port;

	bool ret;

	u8 link_coding_cap;



	aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;

	/* Accessing the connector state is required for vcpi_slots allocation
@@ -238,6 +239,8 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( 


	mst_port = aconnector->port;



	link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);



	if (enable) {



		ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port,
@@ -251,7 +254,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( 
	}



	/* It's OK for this to fail */

	drm_dp_update_payload_part1(mst_mgr, 1);

	drm_dp_update_payload_part1(mst_mgr, (link_coding_cap == DP_CAP_ANSI_128B132B) ? 0:1);



	/* mst_mgr->->payloads are VC payload notify MST branch using DPCD or

	 * AUX message. The sequence is slot 1-63 allocated sequence for each