Unverified Commit 41016fe1 authored by Maxime Ripard's avatar Maxime Ripard
Browse files

drm: Rename plane->state variables in atomic update and disable 



Some drivers are storing the plane->state pointer in atomic_update and
atomic_disable in a variable simply called state, while the state passed
as an argument is called old_state.

In order to ease subsequent reworks and to avoid confusing or
inconsistent names, let's rename those variables to new_state.

This was done using the following coccinelle script, plus some manual
changes for mtk and tegra.

@ plane_atomic_func @
identifier helpers;
identifier func;
@@

(
 static const struct drm_plane_helper_funcs helpers = {
 	...,
 	.atomic_disable = func,
	...,
 };
|
 static const struct drm_plane_helper_funcs helpers = {
 	...,
 	.atomic_update = func,
	...,
 };
)

@ moves_new_state_old_state @
identifier plane_atomic_func.func;
identifier plane;
symbol old_state;
symbol state;
@@

 func(struct drm_plane *plane, struct drm_plane_state *old_state)
 {
 	...
-	struct drm_plane_state *state = plane->state;
+	struct drm_plane_state *new_state = plane->state;
	...
 }

@ depends on moves_new_state_old_state @
identifier plane_atomic_func.func;
identifier plane;
identifier old_state;
symbol state;
@@

 func(struct drm_plane *plane, struct drm_plane_state *old_state)
 {
 	<...
-	state
+	new_state
	...>
 }

@ moves_new_state_oldstate @
identifier plane_atomic_func.func;
identifier plane;
symbol oldstate;
symbol state;
@@

 func(struct drm_plane *plane, struct drm_plane_state *oldstate)
 {
 	...
-	struct drm_plane_state *state = plane->state;
+	struct drm_plane_state *newstate = plane->state;
	...
 }

@ depends on moves_new_state_oldstate @
identifier plane_atomic_func.func;
identifier plane;
identifier old_state;
symbol state;
@@

 func(struct drm_plane *plane, struct drm_plane_state *old_state)
 {
 	<...
-	state
+	newstate
	...>
 }

@ moves_new_state_old_pstate @
identifier plane_atomic_func.func;
identifier plane;
symbol old_pstate;
symbol state;
@@

 func(struct drm_plane *plane, struct drm_plane_state *old_pstate)
 {
 	...
-	struct drm_plane_state *state = plane->state;
+	struct drm_plane_state *new_pstate = plane->state;
	...
 }

@ depends on moves_new_state_old_pstate @
identifier plane_atomic_func.func;
identifier plane;
identifier old_pstate;
symbol state;
@@

 func(struct drm_plane *plane, struct drm_plane_state *old_pstate)
 {
 	<...
-	state
+	new_pstate
	...>
 }

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Acked-by: default avatarThomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20210219120032.260676-8-maxime@cerno.tech
parent e05162c0

drivers/gpu/drm/arm/malidp_planes.c

+17 −17
Original line number Diff line number Diff line
@@ -795,9 +795,9 @@ static void malidp_de_plane_update(struct drm_plane *plane, 
{

	struct malidp_plane *mp;

	struct malidp_plane_state *ms = to_malidp_plane_state(plane->state);

	struct drm_plane_state *state = plane->state;

	u16 pixel_alpha = state->pixel_blend_mode;

	u8 plane_alpha = state->alpha >> 8;

	struct drm_plane_state *new_state = plane->state;

	u16 pixel_alpha = new_state->pixel_blend_mode;

	u8 plane_alpha = new_state->alpha >> 8;

	u32 src_w, src_h, dest_w, dest_h, val;

	int i;

	struct drm_framebuffer *fb = plane->state->fb;
@@ -813,12 +813,12 @@ static void malidp_de_plane_update(struct drm_plane *plane, 
		src_h = fb->height;

	} else {

		/* convert src values from Q16 fixed point to integer */

		src_w = state->src_w >> 16;

		src_h = state->src_h >> 16;

		src_w = new_state->src_w >> 16;

		src_h = new_state->src_h >> 16;

	}



	dest_w = state->crtc_w;

	dest_h = state->crtc_h;

	dest_w = new_state->crtc_w;

	dest_h = new_state->crtc_h;



	val = malidp_hw_read(mp->hwdev, mp->layer->base);

	val = (val & ~LAYER_FORMAT_MASK) | ms->format;
@@ -830,7 +830,7 @@ static void malidp_de_plane_update(struct drm_plane *plane, 
	malidp_de_set_mmu_control(mp, ms);



	malidp_de_set_plane_pitches(mp, ms->n_planes,

				    state->fb->pitches);

				    new_state->fb->pitches);



	if ((plane->state->color_encoding != old_state->color_encoding) ||

	    (plane->state->color_range != old_state->color_range))
@@ -843,8 +843,8 @@ static void malidp_de_plane_update(struct drm_plane *plane, 
	malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h),

			mp->layer->base + MALIDP_LAYER_COMP_SIZE);



	malidp_hw_write(mp->hwdev, LAYER_H_VAL(state->crtc_x) |

			LAYER_V_VAL(state->crtc_y),

	malidp_hw_write(mp->hwdev, LAYER_H_VAL(new_state->crtc_x) |

			LAYER_V_VAL(new_state->crtc_y),

			mp->layer->base + MALIDP_LAYER_OFFSET);



	if (mp->layer->id == DE_SMART) {
@@ -866,19 +866,19 @@ static void malidp_de_plane_update(struct drm_plane *plane, 
	val &= ~LAYER_ROT_MASK;



	/* setup the rotation and axis flip bits */

	if (state->rotation & DRM_MODE_ROTATE_MASK)

	if (new_state->rotation & DRM_MODE_ROTATE_MASK)

		val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) <<

		       LAYER_ROT_OFFSET;

	if (state->rotation & DRM_MODE_REFLECT_X)

	if (new_state->rotation & DRM_MODE_REFLECT_X)

		val |= LAYER_H_FLIP;

	if (state->rotation & DRM_MODE_REFLECT_Y)

	if (new_state->rotation & DRM_MODE_REFLECT_Y)

		val |= LAYER_V_FLIP;



	val &= ~(LAYER_COMP_MASK | LAYER_PMUL_ENABLE | LAYER_ALPHA(0xff));



	if (state->alpha != DRM_BLEND_ALPHA_OPAQUE) {

	if (new_state->alpha != DRM_BLEND_ALPHA_OPAQUE) {

		val |= LAYER_COMP_PLANE;

	} else if (state->fb->format->has_alpha) {

	} else if (new_state->fb->format->has_alpha) {

		/* We only care about blend mode if the format has alpha */

		switch (pixel_alpha) {

		case DRM_MODE_BLEND_PREMULTI:
@@ -892,9 +892,9 @@ static void malidp_de_plane_update(struct drm_plane *plane, 
	val |= LAYER_ALPHA(plane_alpha);



	val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK);

	if (state->crtc) {

	if (new_state->crtc) {

		struct malidp_crtc_state *m =

			to_malidp_crtc_state(state->crtc->state);

			to_malidp_crtc_state(new_state->crtc->state);



		if (m->scaler_config.scale_enable &&

		    m->scaler_config.plane_src_id == mp->layer->id)

drivers/gpu/drm/armada/armada_overlay.c

+53 −51
Original line number Diff line number Diff line
@@ -68,7 +68,7 @@ static inline u32 armada_csc(struct drm_plane_state *state) 
static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane,

	struct drm_plane_state *old_state)

{

	struct drm_plane_state *state = plane->state;

	struct drm_plane_state *new_state = plane->state;

	struct armada_crtc *dcrtc;

	struct armada_regs *regs;

	unsigned int idx;
@@ -76,62 +76,64 @@ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, 


	DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);



	if (!state->fb || WARN_ON(!state->crtc))

	if (!new_state->fb || WARN_ON(!new_state->crtc))

		return;



	DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n",

		plane->base.id, plane->name,

		state->crtc->base.id, state->crtc->name,

		state->fb->base.id,

		old_state->visible, state->visible);

		new_state->crtc->base.id, new_state->crtc->name,

		new_state->fb->base.id,

		old_state->visible, new_state->visible);



	dcrtc = drm_to_armada_crtc(state->crtc);

	dcrtc = drm_to_armada_crtc(new_state->crtc);

	regs = dcrtc->regs + dcrtc->regs_idx;



	idx = 0;

	if (!old_state->visible && state->visible)

	if (!old_state->visible && new_state->visible)

		armada_reg_queue_mod(regs, idx,

				     0, CFG_PDWN16x66 | CFG_PDWN32x66,

				     LCD_SPU_SRAM_PARA1);

	val = armada_src_hw(state);

	val = armada_src_hw(new_state);

	if (armada_src_hw(old_state) != val)

		armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN);

	val = armada_dst_yx(state);

	val = armada_dst_yx(new_state);

	if (armada_dst_yx(old_state) != val)

		armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN);

	val = armada_dst_hw(state);

	val = armada_dst_hw(new_state);

	if (armada_dst_hw(old_state) != val)

		armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN);

	/* FIXME: overlay on an interlaced display */

	if (old_state->src.x1 != state->src.x1 ||

	    old_state->src.y1 != state->src.y1 ||

	    old_state->fb != state->fb ||

	    state->crtc->state->mode_changed) {

	if (old_state->src.x1 != new_state->src.x1 ||

	    old_state->src.y1 != new_state->src.y1 ||

	    old_state->fb != new_state->fb ||

	    new_state->crtc->state->mode_changed) {

		const struct drm_format_info *format;

		u16 src_x;



		armada_reg_queue_set(regs, idx, armada_addr(state, 0, 0),

		armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0),

				     LCD_SPU_DMA_START_ADDR_Y0);

		armada_reg_queue_set(regs, idx, armada_addr(state, 0, 1),

		armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 1),

				     LCD_SPU_DMA_START_ADDR_U0);

		armada_reg_queue_set(regs, idx, armada_addr(state, 0, 2),

		armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 2),

				     LCD_SPU_DMA_START_ADDR_V0);

		armada_reg_queue_set(regs, idx, armada_addr(state, 1, 0),

		armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0),

				     LCD_SPU_DMA_START_ADDR_Y1);

		armada_reg_queue_set(regs, idx, armada_addr(state, 1, 1),

		armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 1),

				     LCD_SPU_DMA_START_ADDR_U1);

		armada_reg_queue_set(regs, idx, armada_addr(state, 1, 2),

		armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 2),

				     LCD_SPU_DMA_START_ADDR_V1);



		val = armada_pitch(state, 0) << 16 | armada_pitch(state, 0);

		val = armada_pitch(new_state, 0) << 16 | armada_pitch(new_state,

								      0);

		armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC);

		val = armada_pitch(state, 1) << 16 | armada_pitch(state, 2);

		val = armada_pitch(new_state, 1) << 16 | armada_pitch(new_state,

								      2);

		armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV);



		cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) |

		      CFG_DMA_MOD(drm_fb_to_armada_fb(state->fb)->mod) |

		cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(new_state->fb)->fmt) |

		      CFG_DMA_MOD(drm_fb_to_armada_fb(new_state->fb)->mod) |

		      CFG_CBSH_ENA;

		if (state->visible)

		if (new_state->visible)

			cfg |= CFG_DMA_ENA;



		/*
@@ -139,28 +141,28 @@ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, 
		 * U/V planes to swap.  Compensate for it by also toggling

		 * the UV swap.

		 */

		format = state->fb->format;

		src_x = state->src.x1 >> 16;

		format = new_state->fb->format;

		src_x = new_state->src.x1 >> 16;

		if (format->num_planes == 1 && src_x & (format->hsub - 1))

			cfg ^= CFG_DMA_MOD(CFG_SWAPUV);

		if (to_armada_plane_state(state)->interlace)

		if (to_armada_plane_state(new_state)->interlace)

			cfg |= CFG_DMA_FTOGGLE;

		cfg_mask = CFG_CBSH_ENA | CFG_DMAFORMAT |

			   CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV |

				       CFG_SWAPYU | CFG_YUV2RGB) |

			   CFG_DMA_FTOGGLE | CFG_DMA_TSTMODE |

			   CFG_DMA_ENA;

	} else if (old_state->visible != state->visible) {

		cfg = state->visible ? CFG_DMA_ENA : 0;

	} else if (old_state->visible != new_state->visible) {

		cfg = new_state->visible ? CFG_DMA_ENA : 0;

		cfg_mask = CFG_DMA_ENA;

	} else {

		cfg = cfg_mask = 0;

	}

	if (drm_rect_width(&old_state->src) != drm_rect_width(&state->src) ||

	    drm_rect_width(&old_state->dst) != drm_rect_width(&state->dst)) {

	if (drm_rect_width(&old_state->src) != drm_rect_width(&new_state->src) ||

	    drm_rect_width(&old_state->dst) != drm_rect_width(&new_state->dst)) {

		cfg_mask |= CFG_DMA_HSMOOTH;

		if (drm_rect_width(&state->src) >> 16 !=

		    drm_rect_width(&state->dst))

		if (drm_rect_width(&new_state->src) >> 16 !=

		    drm_rect_width(&new_state->dst))

			cfg |= CFG_DMA_HSMOOTH;

	}
@@ -168,41 +170,41 @@ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, 
		armada_reg_queue_mod(regs, idx, cfg, cfg_mask,

				     LCD_SPU_DMA_CTRL0);



	val = armada_spu_contrast(state);

	if ((!old_state->visible && state->visible) ||

	val = armada_spu_contrast(new_state);

	if ((!old_state->visible && new_state->visible) ||

	    armada_spu_contrast(old_state) != val)

		armada_reg_queue_set(regs, idx, val, LCD_SPU_CONTRAST);

	val = armada_spu_saturation(state);

	if ((!old_state->visible && state->visible) ||

	val = armada_spu_saturation(new_state);

	if ((!old_state->visible && new_state->visible) ||

	    armada_spu_saturation(old_state) != val)

		armada_reg_queue_set(regs, idx, val, LCD_SPU_SATURATION);

	if (!old_state->visible && state->visible)

	if (!old_state->visible && new_state->visible)

		armada_reg_queue_set(regs, idx, 0x00002000, LCD_SPU_CBSH_HUE);

	val = armada_csc(state);

	if ((!old_state->visible && state->visible) ||

	val = armada_csc(new_state);

	if ((!old_state->visible && new_state->visible) ||

	    armada_csc(old_state) != val)

		armada_reg_queue_mod(regs, idx, val, CFG_CSC_MASK,

				     LCD_SPU_IOPAD_CONTROL);

	val = drm_to_overlay_state(state)->colorkey_yr;

	if ((!old_state->visible && state->visible) ||

	val = drm_to_overlay_state(new_state)->colorkey_yr;

	if ((!old_state->visible && new_state->visible) ||

	    drm_to_overlay_state(old_state)->colorkey_yr != val)

		armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_Y);

	val = drm_to_overlay_state(state)->colorkey_ug;

	if ((!old_state->visible && state->visible) ||

	val = drm_to_overlay_state(new_state)->colorkey_ug;

	if ((!old_state->visible && new_state->visible) ||

	    drm_to_overlay_state(old_state)->colorkey_ug != val)

		armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_U);

	val = drm_to_overlay_state(state)->colorkey_vb;

	if ((!old_state->visible && state->visible) ||

	val = drm_to_overlay_state(new_state)->colorkey_vb;

	if ((!old_state->visible && new_state->visible) ||

	    drm_to_overlay_state(old_state)->colorkey_vb != val)

		armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_V);

	val = drm_to_overlay_state(state)->colorkey_mode;

	if ((!old_state->visible && state->visible) ||

	val = drm_to_overlay_state(new_state)->colorkey_mode;

	if ((!old_state->visible && new_state->visible) ||

	    drm_to_overlay_state(old_state)->colorkey_mode != val)

		armada_reg_queue_mod(regs, idx, val, CFG_CKMODE_MASK |

				     CFG_ALPHAM_MASK | CFG_ALPHA_MASK,

				     LCD_SPU_DMA_CTRL1);

	val = drm_to_overlay_state(state)->colorkey_enable;

	if (((!old_state->visible && state->visible) ||

	val = drm_to_overlay_state(new_state)->colorkey_enable;

	if (((!old_state->visible && new_state->visible) ||

	     drm_to_overlay_state(old_state)->colorkey_enable != val) &&

	    dcrtc->variant->has_spu_adv_reg)

		armada_reg_queue_mod(regs, idx, val, ADV_GRACOLORKEY |

drivers/gpu/drm/armada/armada_plane.c

+32 −31
Original line number Diff line number Diff line
@@ -163,7 +163,7 @@ int armada_drm_plane_atomic_check(struct drm_plane *plane, 
static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane,

	struct drm_plane_state *old_state)

{

	struct drm_plane_state *state = plane->state;

	struct drm_plane_state *new_state = plane->state;

	struct armada_crtc *dcrtc;

	struct armada_regs *regs;

	u32 cfg, cfg_mask, val;
@@ -171,71 +171,72 @@ static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane, 


	DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);



	if (!state->fb || WARN_ON(!state->crtc))

	if (!new_state->fb || WARN_ON(!new_state->crtc))

		return;



	DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n",

		plane->base.id, plane->name,

		state->crtc->base.id, state->crtc->name,

		state->fb->base.id,

		old_state->visible, state->visible);

		new_state->crtc->base.id, new_state->crtc->name,

		new_state->fb->base.id,

		old_state->visible, new_state->visible);



	dcrtc = drm_to_armada_crtc(state->crtc);

	dcrtc = drm_to_armada_crtc(new_state->crtc);

	regs = dcrtc->regs + dcrtc->regs_idx;



	idx = 0;

	if (!old_state->visible && state->visible) {

	if (!old_state->visible && new_state->visible) {

		val = CFG_PDWN64x66;

		if (drm_fb_to_armada_fb(state->fb)->fmt > CFG_420)

		if (drm_fb_to_armada_fb(new_state->fb)->fmt > CFG_420)

			val |= CFG_PDWN256x24;

		armada_reg_queue_mod(regs, idx, 0, val, LCD_SPU_SRAM_PARA1);

	}

	val = armada_src_hw(state);

	val = armada_src_hw(new_state);

	if (armada_src_hw(old_state) != val)

		armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_HPXL_VLN);

	val = armada_dst_yx(state);

	val = armada_dst_yx(new_state);

	if (armada_dst_yx(old_state) != val)

		armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_OVSA_HPXL_VLN);

	val = armada_dst_hw(state);

	val = armada_dst_hw(new_state);

	if (armada_dst_hw(old_state) != val)

		armada_reg_queue_set(regs, idx, val, LCD_SPU_GZM_HPXL_VLN);

	if (old_state->src.x1 != state->src.x1 ||

	    old_state->src.y1 != state->src.y1 ||

	    old_state->fb != state->fb ||

	    state->crtc->state->mode_changed) {

		armada_reg_queue_set(regs, idx, armada_addr(state, 0, 0),

	if (old_state->src.x1 != new_state->src.x1 ||

	    old_state->src.y1 != new_state->src.y1 ||

	    old_state->fb != new_state->fb ||

	    new_state->crtc->state->mode_changed) {

		armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0),

				     LCD_CFG_GRA_START_ADDR0);

		armada_reg_queue_set(regs, idx, armada_addr(state, 1, 0),

		armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0),

				     LCD_CFG_GRA_START_ADDR1);

		armada_reg_queue_mod(regs, idx, armada_pitch(state, 0), 0xffff,

		armada_reg_queue_mod(regs, idx, armada_pitch(new_state, 0),

				     0xffff,

				     LCD_CFG_GRA_PITCH);

	}

	if (old_state->fb != state->fb ||

	    state->crtc->state->mode_changed) {

		cfg = CFG_GRA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) |

		      CFG_GRA_MOD(drm_fb_to_armada_fb(state->fb)->mod);

		if (drm_fb_to_armada_fb(state->fb)->fmt > CFG_420)

	if (old_state->fb != new_state->fb ||

	    new_state->crtc->state->mode_changed) {

		cfg = CFG_GRA_FMT(drm_fb_to_armada_fb(new_state->fb)->fmt) |

		      CFG_GRA_MOD(drm_fb_to_armada_fb(new_state->fb)->mod);

		if (drm_fb_to_armada_fb(new_state->fb)->fmt > CFG_420)

			cfg |= CFG_PALETTE_ENA;

		if (state->visible)

		if (new_state->visible)

			cfg |= CFG_GRA_ENA;

		if (to_armada_plane_state(state)->interlace)

		if (to_armada_plane_state(new_state)->interlace)

			cfg |= CFG_GRA_FTOGGLE;

		cfg_mask = CFG_GRAFORMAT |

			   CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |

				       CFG_SWAPYU | CFG_YUV2RGB) |

			   CFG_PALETTE_ENA | CFG_GRA_FTOGGLE |

			   CFG_GRA_ENA;

	} else if (old_state->visible != state->visible) {

		cfg = state->visible ? CFG_GRA_ENA : 0;

	} else if (old_state->visible != new_state->visible) {

		cfg = new_state->visible ? CFG_GRA_ENA : 0;

		cfg_mask = CFG_GRA_ENA;

	} else {

		cfg = cfg_mask = 0;

	}

	if (drm_rect_width(&old_state->src) != drm_rect_width(&state->src) ||

	    drm_rect_width(&old_state->dst) != drm_rect_width(&state->dst)) {

	if (drm_rect_width(&old_state->src) != drm_rect_width(&new_state->src) ||

	    drm_rect_width(&old_state->dst) != drm_rect_width(&new_state->dst)) {

		cfg_mask |= CFG_GRA_HSMOOTH;

		if (drm_rect_width(&state->src) >> 16 !=

		    drm_rect_width(&state->dst))

		if (drm_rect_width(&new_state->src) >> 16 !=

		    drm_rect_width(&new_state->dst))

			cfg |= CFG_GRA_HSMOOTH;

	}

drivers/gpu/drm/ast/ast_mode.c

+15 −15
Original line number Diff line number Diff line
@@ -573,14 +573,14 @@ ast_primary_plane_helper_atomic_update(struct drm_plane *plane, 
{

	struct drm_device *dev = plane->dev;

	struct ast_private *ast = to_ast_private(dev);

	struct drm_plane_state *state = plane->state;

	struct drm_plane_state *new_state = plane->state;

	struct drm_gem_vram_object *gbo;

	s64 gpu_addr;

	struct drm_framebuffer *fb = state->fb;

	struct drm_framebuffer *fb = new_state->fb;

	struct drm_framebuffer *old_fb = old_state->fb;



	if (!old_fb || (fb->format != old_fb->format)) {

		struct drm_crtc_state *crtc_state = state->crtc->state;

		struct drm_crtc_state *crtc_state = new_state->crtc->state;

		struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);

		struct ast_vbios_mode_info *vbios_mode_info = &ast_crtc_state->vbios_mode_info;
@@ -793,9 +793,9 @@ ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, 
				      struct drm_plane_state *old_state)

{

	struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane);

	struct drm_plane_state *state = plane->state;

	struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state);

	struct drm_framebuffer *fb = state->fb;

	struct drm_plane_state *new_state = plane->state;

	struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(new_state);

	struct drm_framebuffer *fb = new_state->fb;

	struct ast_private *ast = to_ast_private(plane->dev);

	struct dma_buf_map dst_map =

		ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].map;
@@ -820,7 +820,7 @@ ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, 


	ast_update_cursor_image(dst, src, fb->width, fb->height);



	if (state->fb != old_state->fb) {

	if (new_state->fb != old_state->fb) {

		ast_set_cursor_base(ast, dst_off);



		++ast_cursor_plane->next_hwc_index;
@@ -831,25 +831,25 @@ ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, 
	 * Update location in HWC signature and registers.

	 */



	writel(state->crtc_x, sig + AST_HWC_SIGNATURE_X);

	writel(state->crtc_y, sig + AST_HWC_SIGNATURE_Y);

	writel(new_state->crtc_x, sig + AST_HWC_SIGNATURE_X);

	writel(new_state->crtc_y, sig + AST_HWC_SIGNATURE_Y);



	offset_x = AST_MAX_HWC_WIDTH - fb->width;

	offset_y = AST_MAX_HWC_HEIGHT - fb->height;



	if (state->crtc_x < 0) {

		x_offset = (-state->crtc_x) + offset_x;

	if (new_state->crtc_x < 0) {

		x_offset = (-new_state->crtc_x) + offset_x;

		x = 0;

	} else {

		x_offset = offset_x;

		x = state->crtc_x;

		x = new_state->crtc_x;

	}

	if (state->crtc_y < 0) {

		y_offset = (-state->crtc_y) + offset_y;

	if (new_state->crtc_y < 0) {

		y_offset = (-new_state->crtc_y) + offset_y;

		y = 0;

	} else {

		y_offset = offset_y;

		y = state->crtc_y;

		y = new_state->crtc_y;

	}



	ast_set_cursor_location(ast, x, y, x_offset, y_offset);

drivers/gpu/drm/exynos/exynos_drm_plane.c

+3 −3
Original line number Diff line number Diff line
@@ -254,11 +254,11 @@ static int exynos_plane_atomic_check(struct drm_plane *plane, 
static void exynos_plane_atomic_update(struct drm_plane *plane,

				       struct drm_plane_state *old_state)

{

	struct drm_plane_state *state = plane->state;

	struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(state->crtc);

	struct drm_plane_state *new_state = plane->state;

	struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(new_state->crtc);

	struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);



	if (!state->crtc)

	if (!new_state->crtc)

		return;



	if (exynos_crtc->ops->update_plane)