Commit 40b95583 authored by Pratyush Yadav's avatar Pratyush Yadav Committed by Vinod Koul
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phy: dt-bindings: Convert Cadence DPHY binding to YAML

parent 41d393aa
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Cadence DPHY
============

Cadence DPHY block.

Required properties:
- compatible: should be set to "cdns,dphy".
- reg: physical base address and length of the DPHY registers.
- clocks: DPHY reference clocks.
- clock-names: must contain "psm" and "pll_ref".
- #phy-cells: must be set to 0.

Example:
	dphy0: dphy@fd0e0000{
		compatible = "cdns,dphy";
		reg = <0x0 0xfd0e0000 0x0 0x1000>;
		clocks = <&psm_clk>, <&pll_ref_clk>;
		clock-names = "psm", "pll_ref";
		#phy-cells = <0>;
	};
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/cdns,dphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence DPHY Device Tree Bindings

maintainers:
  - Pratyush Yadav <p.yadav@ti.com>

properties:
  compatible:
    items:
      - const: cdns,dphy

  reg:
    maxItems: 1

  clocks:
    items:
      - description: PMA state machine clock
      - description: PLL reference clock

  clock-names:
    items:
      - const: psm
      - const: pll_ref

  "#phy-cells":
    const: 0

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - "#phy-cells"

additionalProperties: false

examples:
  - |

    dphy0: phy@fd0e0000{
        compatible = "cdns,dphy";
        reg = <0xfd0e0000 0x1000>;
        clocks = <&psm_clk>, <&pll_ref_clk>;
        clock-names = "psm", "pll_ref";
        #phy-cells = <0>;
    };