Commit 40b4ffe5 authored by Artur Weber's avatar Artur Weber Committed by Krzysztof Kozlowski
Browse files

clk: samsung: Re-add support for Exynos4212 CPU clock 



Support for the Exynos4212 SoC was originally dropped as there were
no boards using it. We will be adding a device that uses it, so add
it back.

This reverts commit c9194fb6.

Signed-off-by: default avatarArtur Weber <aweber.kernel@gmail.com>
Link: https://lore.kernel.org/r/20230501195525.6268-7-aweber.kernel@gmail.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 48b35973

drivers/clk/samsung/clk-exynos4.c

+39 −5
Original line number Diff line number Diff line
@@ -138,7 +138,8 @@ 
/* the exynos4 soc type */

enum exynos4_soc {

	EXYNOS4210,

	EXYNOS4X12,

	EXYNOS4212,

	EXYNOS4412,

};



/* list of PLLs to be registered */
@@ -1205,6 +1206,24 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = { 
	{  0 },

};



static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {

	{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },

	{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },

	{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },

	{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },

	{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },

	{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },

	{  900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },

	{  800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },

	{  700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },

	{  600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },

	{  500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },

	{  400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },

	{  300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },

	{  200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },

	{  0 },

};



#define E4412_CPU_DIV1(cores, hpm, copy)				\

		(((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
@@ -1233,6 +1252,11 @@ static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = { 
			CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4210_armclk_d),

};



static const struct samsung_cpu_clock exynos4212_cpu_clks[] __initconst = {

	CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,

		CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4212_armclk_d),

};



static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {

	CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,

			CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4412_armclk_d),
@@ -1326,11 +1350,15 @@ static void __init exynos4_clk_init(struct device_node *np, 
		samsung_clk_register_fixed_factor(ctx,

			exynos4x12_fixed_factor_clks,

			ARRAY_SIZE(exynos4x12_fixed_factor_clks));

		if (soc == EXYNOS4412)

			samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,

					ARRAY_SIZE(exynos4412_cpu_clks));

		else

			samsung_clk_register_cpu(ctx, exynos4212_cpu_clks,

					ARRAY_SIZE(exynos4212_cpu_clks));

	}



	if (soc == EXYNOS4X12)

	if (soc == EXYNOS4212 || soc == EXYNOS4412)

		exynos4x12_core_down_clock();



	samsung_clk_extended_sleep_init(reg_base,
@@ -1363,8 +1391,14 @@ static void __init exynos4210_clk_init(struct device_node *np) 
}

CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);



static void __init exynos4212_clk_init(struct device_node *np)

{

	exynos4_clk_init(np, EXYNOS4212);

}

CLK_OF_DECLARE(exynos4212_clk, "samsung,exynos4212-clock", exynos4212_clk_init);



static void __init exynos4412_clk_init(struct device_node *np)

{

	exynos4_clk_init(np, EXYNOS4X12);

	exynos4_clk_init(np, EXYNOS4412);

}

CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);