Commit 40aacb31 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'loongarch-fixes-6.3-1' of... 

Merge tag 'loongarch-fixes-6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson

Pull LoongArch fixes from Huacai Chen:
 "Some bug fixes, some build fixes, a comment fix and a trivial cleanup"

* tag 'loongarch-fixes-6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson:
  tools/loongarch: Use __SIZEOF_LONG__ to define __BITS_PER_LONG
  LoongArch: Replace hard-coded values in comments with VALEN
  LoongArch: Clean up plat_swiotlb_setup() related code
  LoongArch: Check unwind_error() in arch_stack_walk()
  LoongArch: Adjust user_regset_copyin parameter to the correct offset
  LoongArch: Adjust user_watch_state for explicit alignment
  LoongArch: module: set section addresses to 0x0
  LoongArch: Mark 3 symbol exports as non-GPL
  LoongArch: Enable PG when wakeup from suspend
  LoongArch: Fix _CONST64_(x) as unsigned
  LoongArch: Fix build error if CONFIG_SUSPEND is not set
  LoongArch: Fix probing of the CRC32 feature
  LoongArch: Make WriteCombine configurable for ioremap()
parents af67688d b5533e99

Documentation/admin-guide/kernel-parameters.rst

+1 −0
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@@ -128,6 +128,7 @@ parameter is applicable:: 
	KVM	Kernel Virtual Machine support is enabled.

	LIBATA  Libata driver is enabled

	LP	Printer support is enabled.

	LOONGARCH LoongArch architecture is enabled.

	LOOP	Loopback device support is enabled.

	M68k	M68k architecture is enabled.

			These options have more detailed description inside of

Documentation/admin-guide/kernel-parameters.txt

+6 −0
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@@ -6933,6 +6933,12 @@ 
			When enabled, memory and cache locality will be

			impacted.



	writecombine=	[LOONGARCH] Control the MAT (Memory Access Type) of

			ioremap_wc().



			on   - Enable writecombine, use WUC for ioremap_wc()

			off  - Disable writecombine, use SUC for ioremap_wc()



	x2apic_phys	[X86-64,APIC] Use x2apic physical mode instead of

			default x2apic cluster mode on platforms

			supporting x2apic.

arch/loongarch/Kconfig

+16 −0
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@@ -447,6 +447,22 @@ config ARCH_IOREMAP 
	  protection support. However, you can enable LoongArch DMW-based

	  ioremap() for better performance.



config ARCH_WRITECOMBINE

	bool "Enable WriteCombine (WUC) for ioremap()"

	help

	  LoongArch maintains cache coherency in hardware, but when paired

	  with LS7A chipsets the WUC attribute (Weak-ordered UnCached, which

	  is similar to WriteCombine) is out of the scope of cache coherency

	  machanism for PCIe devices (this is a PCIe protocol violation, which

	  may be fixed in newer chipsets).



	  This means WUC can only used for write-only memory regions now, so

	  this option is disabled by default, making WUC silently fallback to

	  SUC for ioremap(). You can enable this option if the kernel is ensured

	  to run on hardware without this bug.



	  You can override this setting via writecombine=on/off boot parameter.



config ARCH_STRICT_ALIGN

	bool "Enable -mstrict-align to prevent unaligned accesses" if EXPERT

	default y

arch/loongarch/include/asm/acpi.h

+3 −0
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@@ -41,8 +41,11 @@ extern void loongarch_suspend_enter(void); 


static inline unsigned long acpi_get_wakeup_address(void)

{

#ifdef CONFIG_SUSPEND

	extern void loongarch_wakeup_start(void);

	return (unsigned long)loongarch_wakeup_start;

#endif

	return 0UL;

}



#endif /* _ASM_LOONGARCH_ACPI_H */

arch/loongarch/include/asm/addrspace.h

+2 −2
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@@ -71,9 +71,9 @@ extern unsigned long vm_map_base; 
#define _ATYPE32_	int

#define _ATYPE64_	__s64

#ifdef CONFIG_64BIT

#define _CONST64_(x)	x ## L

#define _CONST64_(x)	x ## UL

#else

#define _CONST64_(x)	x ## LL

#define _CONST64_(x)	x ## ULL

#endif

#endif