Commit 40a645f7 authored by Srujana Challa's avatar Srujana Challa Committed by Herbert Xu
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crypto: octeontx2 - add support for CPT operations on CN10K 



CPT result format had changed for CN10K HW to accommodate more
fields. This patch adds support to use new result format and
new LMTST lines for CPT operations on CN10K platform.

Signed-off-by: default avatarSrujana Challa <schalla@marvell.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent eb33cd91

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

+42 −2
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright (C) 2021 Marvell. */



#include <linux/soc/marvell/octeontx2/asm.h>

#include "otx2_cptpf.h"

#include "otx2_cptvf.h"

#include "otx2_cptlf.h"

#include "cn10k_cpt.h"



static struct cpt_hw_ops otx2_hw_ops = {

	.send_cmd = otx2_cpt_send_cmd,

	.cpt_get_compcode = otx2_cpt_get_compcode,

	.cpt_get_uc_compcode = otx2_cpt_get_uc_compcode,

};



static struct cpt_hw_ops cn10k_hw_ops = {

	.send_cmd = cn10k_cpt_send_cmd,

	.cpt_get_compcode = cn10k_cpt_get_compcode,

	.cpt_get_uc_compcode = cn10k_cpt_get_uc_compcode,

};



void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num,

			struct otx2_cptlf_info *lf)

{

	void __iomem *lmtline = lf->lmtline;

	u64 val = (lf->slot & 0x7FF);

	u64 tar_addr = 0;



	/* tar_addr<6:4> = Size of first LMTST - 1 in units of 128b. */

	tar_addr |= (__force u64)lf->ioreg |

		    (((OTX2_CPT_INST_SIZE/16) - 1) & 0x7) << 4;

	/*

	 * Make sure memory areas pointed in CPT_INST_S

	 * are flushed before the instruction is sent to CPT

	 */

	dma_wmb();



	/* Copy CPT command to LMTLINE */

	memcpy_toio(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE);

	cn10k_lmt_flush(val, tar_addr);

}



int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf)

{

	struct pci_dev *pdev = cptpf->pdev;

	resource_size_t size;

	u64 lmt_base;



	if (!test_bit(CN10K_LMTST, &cptpf->cap_flag))

	if (!test_bit(CN10K_LMTST, &cptpf->cap_flag)) {

		cptpf->lfs.ops = &otx2_hw_ops;

		return 0;

	}



	cptpf->lfs.ops = &cn10k_hw_ops;

	lmt_base = readq(cptpf->reg_base + RVU_PF_LMTLINE_ADDR);

	if (!lmt_base) {

		dev_err(&pdev->dev, "PF LMTLINE address not configured\n");
@@ -37,9 +74,12 @@ int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf) 
	struct pci_dev *pdev = cptvf->pdev;

	resource_size_t offset, size;



	if (!test_bit(CN10K_LMTST, &cptvf->cap_flag))

	if (!test_bit(CN10K_LMTST, &cptvf->cap_flag)) {

		cptvf->lfs.ops = &otx2_hw_ops;

		return 0;

	}



	cptvf->lfs.ops = &cn10k_hw_ops;

	offset = pci_resource_start(pdev, PCI_MBOX_BAR_NUM);

	size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);

	/* Map VF LMILINE region */

drivers/crypto/marvell/octeontx2/cn10k_cpt.h

+23 −0
Original line number Diff line number Diff line
@@ -4,9 +4,32 @@ 
#ifndef __CN10K_CPT_H

#define __CN10K_CPT_H



#include "otx2_cpt_common.h"

#include "otx2_cptpf.h"

#include "otx2_cptvf.h"



static inline u8 cn10k_cpt_get_compcode(union otx2_cpt_res_s *result)

{

	return ((struct cn10k_cpt_res_s *)result)->compcode;

}



static inline u8 cn10k_cpt_get_uc_compcode(union otx2_cpt_res_s *result)

{

	return ((struct cn10k_cpt_res_s *)result)->uc_compcode;

}



static inline u8 otx2_cpt_get_compcode(union otx2_cpt_res_s *result)

{

	return ((struct cn9k_cpt_res_s *)result)->compcode;

}



static inline u8 otx2_cpt_get_uc_compcode(union otx2_cpt_res_s *result)

{

	return ((struct cn9k_cpt_res_s *)result)->uc_compcode;

}



void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num,

			struct otx2_cptlf_info *lf);

int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf);

int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf);

drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h

+11 −2
Original line number Diff line number Diff line
@@ -138,7 +138,7 @@ enum otx2_cpt_comp_e { 
	OTX2_CPT_COMP_E_FAULT = 0x02,

	OTX2_CPT_COMP_E_HWERR = 0x04,

	OTX2_CPT_COMP_E_INSTERR = 0x05,

	OTX2_CPT_COMP_E_LAST_ENTRY = 0x06

	OTX2_CPT_COMP_E_WARN = 0x06

};



/*
@@ -269,13 +269,22 @@ union otx2_cpt_inst_s { 
union otx2_cpt_res_s {

	u64 u[2];



	struct {

	struct cn9k_cpt_res_s {

		u64 compcode:8;

		u64 uc_compcode:8;

		u64 doneint:1;

		u64 reserved_17_63:47;

		u64 reserved_64_127;

	} s;



	struct cn10k_cpt_res_s {

		u64 compcode:7;

		u64 doneint:1;

		u64 uc_compcode:8;

		u64 rlen:16;

		u64 spi:32;

		u64 esn;

	} cn10k;

};



/*

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

+7 −2
Original line number Diff line number Diff line
@@ -379,9 +379,14 @@ int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_mask, int pri, 
	for (slot = 0; slot < lfs->lfs_num; slot++) {

		lfs->lf[slot].lfs = lfs;

		lfs->lf[slot].slot = slot;

		if (lfs->lmt_base)

			lfs->lf[slot].lmtline = lfs->lmt_base +

						(slot * LMTLINE_SIZE);

		else

			lfs->lf[slot].lmtline = lfs->reg_base +

				OTX2_CPT_RVU_FUNC_ADDR_S(BLKADDR_LMT, slot,

						 OTX2_CPT_LMT_LF_LMTLINEX(0));



		lfs->lf[slot].ioreg = lfs->reg_base +

			OTX2_CPT_RVU_FUNC_ADDR_S(BLKADDR_CPT0, slot,

						 OTX2_CPT_LF_NQX(0));

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

+8 −0
Original line number Diff line number Diff line
@@ -84,6 +84,13 @@ struct otx2_cptlf_info { 
	struct otx2_cptlf_wqe *wqe;       /* Tasklet work info */

};



struct cpt_hw_ops {

	void (*send_cmd)(union otx2_cpt_inst_s *cptinst, u32 insts_num,

			 struct otx2_cptlf_info *lf);

	u8 (*cpt_get_compcode)(union otx2_cpt_res_s *result);

	u8 (*cpt_get_uc_compcode)(union otx2_cpt_res_s *result);

};



struct otx2_cptlfs_info {

	/* Registers start address of VF/PF LFs are attached to */

	void __iomem *reg_base;
@@ -92,6 +99,7 @@ struct otx2_cptlfs_info { 
	struct pci_dev *pdev;   /* Device LFs are attached to */

	struct otx2_cptlf_info lf[OTX2_CPT_MAX_LFS_NUM];

	struct otx2_mbox *mbox;

	struct cpt_hw_ops *ops;

	u8 are_lfs_attached;	/* Whether CPT LFs are attached */

	u8 lfs_num;		/* Number of CPT LFs */

	u8 kcrypto_eng_grp_num;	/* Kernel crypto engine group number */