Commit 4098ced4 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'brport-flags' 



Vladimir Oltean says:

====================
Cleanup in brport flags switchdev offload for DSA

The initial goal of this series was to have better support for
standalone ports mode on the DSA drivers like ocelot/felix and sja1105.
This turned out to require some API adjustments in both directions:
to the information presented to and by the switchdev notifier, and to
the API presented to the switch drivers by the DSA layer.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents b0aae0bd 4d942354

drivers/net/dsa/b53/b53_common.c

+64 −27
Original line number Diff line number Diff line
@@ -510,6 +510,39 @@ void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 
}

EXPORT_SYMBOL(b53_imp_vlan_setup);



static void b53_port_set_ucast_flood(struct b53_device *dev, int port,

				     bool unicast)

{

	u16 uc;



	b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);

	if (unicast)

		uc |= BIT(port);

	else

		uc &= ~BIT(port);

	b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);

}



static void b53_port_set_mcast_flood(struct b53_device *dev, int port,

				     bool multicast)

{

	u16 mc;



	b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);

	if (multicast)

		mc |= BIT(port);

	else

		mc &= ~BIT(port);

	b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);



	b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);

	if (multicast)

		mc |= BIT(port);

	else

		mc &= ~BIT(port);

	b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);

}



int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)

{

	struct b53_device *dev = ds->priv;
@@ -522,7 +555,8 @@ int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 


	cpu_port = dsa_to_port(ds, port)->cpu_dp->index;



	b53_br_egress_floods(ds, port, true, true);

	b53_port_set_ucast_flood(dev, port, true);

	b53_port_set_mcast_flood(dev, port, true);



	if (dev->ops->irq_enable)

		ret = dev->ops->irq_enable(dev, port);
@@ -655,7 +689,8 @@ static void b53_enable_cpu_port(struct b53_device *dev, int port) 


	b53_brcm_hdr_setup(dev->ds, port);



	b53_br_egress_floods(dev->ds, port, true, true);

	b53_port_set_ucast_flood(dev, port, true);

	b53_port_set_mcast_flood(dev, port, true);

}



static void b53_enable_mib(struct b53_device *dev)
@@ -1916,37 +1951,37 @@ void b53_br_fast_age(struct dsa_switch *ds, int port) 
}

EXPORT_SYMBOL(b53_br_fast_age);



int b53_br_egress_floods(struct dsa_switch *ds, int port,

			 bool unicast, bool multicast)

static int b53_br_flags_pre(struct dsa_switch *ds, int port,

			    struct switchdev_brport_flags flags,

			    struct netlink_ext_ack *extack)

{

	struct b53_device *dev = ds->priv;

	u16 uc, mc;



	b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);

	if (unicast)

		uc |= BIT(port);

	else

		uc &= ~BIT(port);

	b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);

	if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD))

		return -EINVAL;



	b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);

	if (multicast)

		mc |= BIT(port);

	else

		mc &= ~BIT(port);

	b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);

	return 0;

}



	b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);

	if (multicast)

		mc |= BIT(port);

	else

		mc &= ~BIT(port);

	b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);

static int b53_br_flags(struct dsa_switch *ds, int port,

			struct switchdev_brport_flags flags,

			struct netlink_ext_ack *extack)

{

	if (flags.mask & BR_FLOOD)

		b53_port_set_ucast_flood(ds->priv, port,

					 !!(flags.val & BR_FLOOD));

	if (flags.mask & BR_MCAST_FLOOD)

		b53_port_set_mcast_flood(ds->priv, port,

					 !!(flags.val & BR_MCAST_FLOOD));



	return 0;

}



static int b53_set_mrouter(struct dsa_switch *ds, int port, bool mrouter,

			   struct netlink_ext_ack *extack)

{

	b53_port_set_mcast_flood(ds->priv, port, mrouter);



	return 0;

}

EXPORT_SYMBOL(b53_br_egress_floods);



static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)

{
@@ -2187,9 +2222,11 @@ static const struct dsa_switch_ops b53_switch_ops = { 
	.set_mac_eee		= b53_set_mac_eee,

	.port_bridge_join	= b53_br_join,

	.port_bridge_leave	= b53_br_leave,

	.port_pre_bridge_flags	= b53_br_flags_pre,

	.port_bridge_flags	= b53_br_flags,

	.port_set_mrouter	= b53_set_mrouter,

	.port_stp_state_set	= b53_br_set_stp_state,

	.port_fast_age		= b53_br_fast_age,

	.port_egress_floods	= b53_br_egress_floods,

	.port_vlan_filtering	= b53_vlan_filtering,

	.port_vlan_add		= b53_vlan_add,

	.port_vlan_del		= b53_vlan_del,

drivers/net/dsa/b53/b53_priv.h

+0 −2
Original line number Diff line number Diff line
@@ -326,8 +326,6 @@ int b53_br_join(struct dsa_switch *ds, int port, struct net_device *bridge); 
void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *bridge);

void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state);

void b53_br_fast_age(struct dsa_switch *ds, int port);

int b53_br_egress_floods(struct dsa_switch *ds, int port,

			 bool unicast, bool multicast);

int b53_setup_devlink_resources(struct dsa_switch *ds);

void b53_port_event(struct dsa_switch *ds, int port);

void b53_phylink_validate(struct dsa_switch *ds, int port,

drivers/net/dsa/mv88e6xxx/chip.c

+127 −36
Original line number Diff line number Diff line
@@ -2434,12 +2434,20 @@ static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 
{

	struct dsa_switch *ds = chip->ds;

	bool flood;

	int err;



	/* Upstream ports flood frames with unknown unicast or multicast DA */

	flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);

	if (chip->info->ops->port_set_egress_floods)

		return chip->info->ops->port_set_egress_floods(chip, port,

							       flood, flood);

	if (chip->info->ops->port_set_ucast_flood) {

		err = chip->info->ops->port_set_ucast_flood(chip, port, flood);

		if (err)

			return err;

	}

	if (chip->info->ops->port_set_mcast_flood) {

		err = chip->info->ops->port_set_mcast_flood(chip, port, flood);

		if (err)

			return err;

	}



	return 0;

}
@@ -3239,7 +3247,8 @@ static const struct mv88e6xxx_ops mv88e6085_ops = { 
	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,

	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_limit = mv88e6097_port_pause_limit,
@@ -3278,7 +3287,8 @@ static const struct mv88e6xxx_ops mv88e6095_ops = { 
	.port_sync_link = mv88e6185_port_sync_link,

	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,

	.port_set_frame_mode = mv88e6085_port_set_frame_mode,

	.port_set_egress_floods = mv88e6185_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6185_port_set_forward_unknown,

	.port_set_mcast_flood = mv88e6185_port_set_default_forward,

	.port_set_upstream_port = mv88e6095_port_set_upstream_port,

	.port_get_cmode = mv88e6185_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,
@@ -3313,7 +3323,8 @@ static const struct mv88e6xxx_ops mv88e6097_ops = { 
	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,

	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,

	.port_pause_limit = mv88e6097_port_pause_limit,
@@ -3357,7 +3368,8 @@ static const struct mv88e6xxx_ops mv88e6123_ops = { 
	.port_sync_link = mv88e6xxx_port_sync_link,

	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,

	.port_set_frame_mode = mv88e6085_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_get_cmode = mv88e6185_port_get_cmode,
@@ -3393,7 +3405,8 @@ static const struct mv88e6xxx_ops mv88e6131_ops = { 
	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,

	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6185_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6185_port_set_forward_unknown,

	.port_set_mcast_flood = mv88e6185_port_set_default_forward,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_upstream_port = mv88e6095_port_set_upstream_port,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
@@ -3437,7 +3450,8 @@ static const struct mv88e6xxx_ops mv88e6141_ops = { 
	.port_max_speed_mode = mv88e6341_port_max_speed_mode,

	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
@@ -3487,7 +3501,8 @@ static const struct mv88e6xxx_ops mv88e6161_ops = { 
	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,

	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
@@ -3565,7 +3580,8 @@ static const struct mv88e6xxx_ops mv88e6171_ops = { 
	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,

	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
@@ -3609,7 +3625,8 @@ static const struct mv88e6xxx_ops mv88e6172_ops = { 
	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_policy = mv88e6352_port_set_policy,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
@@ -3660,7 +3677,8 @@ static const struct mv88e6xxx_ops mv88e6175_ops = { 
	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,

	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
@@ -3704,7 +3722,8 @@ static const struct mv88e6xxx_ops mv88e6176_ops = { 
	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_policy = mv88e6352_port_set_policy,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
@@ -3755,7 +3774,8 @@ static const struct mv88e6xxx_ops mv88e6185_ops = { 
	.port_sync_link = mv88e6185_port_sync_link,

	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,

	.port_set_frame_mode = mv88e6085_port_set_frame_mode,

	.port_set_egress_floods = mv88e6185_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6185_port_set_forward_unknown,

	.port_set_mcast_flood = mv88e6185_port_set_default_forward,

	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,

	.port_set_upstream_port = mv88e6095_port_set_upstream_port,

	.port_set_pause = mv88e6185_port_set_pause,
@@ -3800,7 +3820,8 @@ static const struct mv88e6xxx_ops mv88e6190_ops = { 
	.port_tag_remap = mv88e6390_port_tag_remap,

	.port_set_policy = mv88e6352_port_set_policy,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_pause_limit = mv88e6390_port_pause_limit,
@@ -3860,7 +3881,8 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = { 
	.port_tag_remap = mv88e6390_port_tag_remap,

	.port_set_policy = mv88e6352_port_set_policy,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_pause_limit = mv88e6390_port_pause_limit,
@@ -3919,7 +3941,8 @@ static const struct mv88e6xxx_ops mv88e6191_ops = { 
	.port_max_speed_mode = mv88e6390_port_max_speed_mode,

	.port_tag_remap = mv88e6390_port_tag_remap,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_pause_limit = mv88e6390_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
@@ -3979,7 +4002,8 @@ static const struct mv88e6xxx_ops mv88e6240_ops = { 
	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_policy = mv88e6352_port_set_policy,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
@@ -4037,7 +4061,8 @@ static const struct mv88e6xxx_ops mv88e6250_ops = { 
	.port_set_speed_duplex = mv88e6250_port_set_speed_duplex,

	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_limit = mv88e6097_port_pause_limit,
@@ -4077,7 +4102,8 @@ static const struct mv88e6xxx_ops mv88e6290_ops = { 
	.port_tag_remap = mv88e6390_port_tag_remap,

	.port_set_policy = mv88e6352_port_set_policy,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_pause_limit = mv88e6390_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
@@ -4136,7 +4162,8 @@ static const struct mv88e6xxx_ops mv88e6320_ops = { 
	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,

	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
@@ -4179,7 +4206,8 @@ static const struct mv88e6xxx_ops mv88e6321_ops = { 
	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,

	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
@@ -4222,7 +4250,8 @@ static const struct mv88e6xxx_ops mv88e6341_ops = { 
	.port_max_speed_mode = mv88e6341_port_max_speed_mode,

	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
@@ -4275,7 +4304,8 @@ static const struct mv88e6xxx_ops mv88e6350_ops = { 
	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,

	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
@@ -4316,7 +4346,8 @@ static const struct mv88e6xxx_ops mv88e6351_ops = { 
	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,

	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
@@ -4362,7 +4393,8 @@ static const struct mv88e6xxx_ops mv88e6352_ops = { 
	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_policy = mv88e6352_port_set_policy,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
@@ -4424,7 +4456,8 @@ static const struct mv88e6xxx_ops mv88e6390_ops = { 
	.port_tag_remap = mv88e6390_port_tag_remap,

	.port_set_policy = mv88e6352_port_set_policy,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
@@ -4488,7 +4521,8 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = { 
	.port_tag_remap = mv88e6390_port_tag_remap,

	.port_set_policy = mv88e6352_port_set_policy,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
@@ -5364,17 +5398,72 @@ static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 
	mutex_unlock(&chip->reg_lock);

}



static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,

					 bool unicast, bool multicast)

static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,

					   struct switchdev_brport_flags flags,

					   struct netlink_ext_ack *extack)

{

	struct mv88e6xxx_chip *chip = ds->priv;

	const struct mv88e6xxx_ops *ops;



	if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD))

		return -EINVAL;



	ops = chip->info->ops;



	if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)

		return -EINVAL;



	if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)

		return -EINVAL;



	return 0;

}



static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,

				       struct switchdev_brport_flags flags,

				       struct netlink_ext_ack *extack)

{

	struct mv88e6xxx_chip *chip = ds->priv;

	int err = -EOPNOTSUPP;



	mv88e6xxx_reg_lock(chip);

	if (chip->info->ops->port_set_egress_floods)

		err = chip->info->ops->port_set_egress_floods(chip, port,

							      unicast,



	if (flags.mask & BR_FLOOD) {

		bool unicast = !!(flags.val & BR_FLOOD);



		err = chip->info->ops->port_set_ucast_flood(chip, port,

							    unicast);

		if (err)

			goto out;

	}



	if (flags.mask & BR_MCAST_FLOOD) {

		bool multicast = !!(flags.val & BR_MCAST_FLOOD);



		err = chip->info->ops->port_set_mcast_flood(chip, port,

							    multicast);

		if (err)

			goto out;

	}



out:

	mv88e6xxx_reg_unlock(chip);



	return err;

}



static int mv88e6xxx_port_set_mrouter(struct dsa_switch *ds, int port,

				      bool mrouter,

				      struct netlink_ext_ack *extack)

{

	struct mv88e6xxx_chip *chip = ds->priv;

	int err;



	if (!chip->info->ops->port_set_mcast_flood)

		return -EOPNOTSUPP;



	mv88e6xxx_reg_lock(chip);

	err = chip->info->ops->port_set_mcast_flood(chip, port, mrouter);

	mv88e6xxx_reg_unlock(chip);



	return err;
@@ -5678,7 +5767,9 @@ static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 
	.set_ageing_time	= mv88e6xxx_set_ageing_time,

	.port_bridge_join	= mv88e6xxx_port_bridge_join,

	.port_bridge_leave	= mv88e6xxx_port_bridge_leave,

	.port_egress_floods	= mv88e6xxx_port_egress_floods,

	.port_pre_bridge_flags	= mv88e6xxx_port_pre_bridge_flags,

	.port_bridge_flags	= mv88e6xxx_port_bridge_flags,

	.port_set_mrouter	= mv88e6xxx_port_set_mrouter,

	.port_stp_state_set	= mv88e6xxx_port_stp_state_set,

	.port_fast_age		= mv88e6xxx_port_fast_age,

	.port_vlan_filtering	= mv88e6xxx_port_vlan_filtering,

drivers/net/dsa/mv88e6xxx/chip.h

+4 −2
Original line number Diff line number Diff line
@@ -454,8 +454,10 @@ struct mv88e6xxx_ops { 


	int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,

				   enum mv88e6xxx_frame_mode mode);

	int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,

				      bool unicast, bool multicast);

	int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port,

				    bool unicast);

	int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port,

				    bool multicast);

	int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,

				   u16 etype);

	int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,

drivers/net/dsa/mv88e6xxx/port.c

+26 −26
Original line number Diff line number Diff line
@@ -789,7 +789,7 @@ int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 
	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);

}



static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,

int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,

				       int port, bool unicast)

{

	int err;
@@ -807,8 +807,8 @@ static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, 
	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);

}



int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,

				     bool unicast, bool multicast)

int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port,

				   bool unicast)

{

	int err;

	u16 reg;
@@ -817,16 +817,28 @@ int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 
	if (err)

		return err;



	reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK;

	if (unicast)

		reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC;

	else

		reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC;



	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);

}



int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port,

				   bool multicast)

{

	int err;

	u16 reg;



	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);

	if (err)

		return err;



	if (unicast && multicast)

		reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA;

	else if (unicast)

		reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA;

	else if (multicast)

		reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA;

	if (multicast)

		reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC;

	else

		reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA;

		reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC;



	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);

}
@@ -1013,7 +1025,7 @@ static const char * const mv88e6xxx_port_8021q_mode_names[] = { 
	[MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure",

};



static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,

int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,

				       int port, bool multicast)

{

	int err;
@@ -1031,18 +1043,6 @@ static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, 
	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);

}



int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,

				     bool unicast, bool multicast)

{

	int err;



	err = mv88e6185_port_set_forward_unknown(chip, port, unicast);

	if (err)

		return err;



	return mv88e6185_port_set_default_forward(chip, port, multicast);

}



int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,

				     int upstream_port)

{