Commit 4090871d authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvmarm-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD 

KVM/arm64 updates for 6.3

 - Provide a virtual cache topology to the guest to avoid
   inconsistencies with migration on heterogenous systems. Non secure
   software has no practical need to traverse the caches by set/way in
   the first place.

 - Add support for taking stage-2 access faults in parallel. This was an
   accidental omission in the original parallel faults implementation,
   but should provide a marginal improvement to machines w/o FEAT_HAFDBS
   (such as hardware from the fruit company).

 - A preamble to adding support for nested virtualization to KVM,
   including vEL2 register state, rudimentary nested exception handling
   and masking unsupported features for nested guests.

 - Fixes to the PSCI relay that avoid an unexpected host SVE trap when
   resuming a CPU when running pKVM.

 - VGIC maintenance interrupt support for the AIC

 - Improvements to the arch timer emulation, primarily aimed at reducing
   the trap overhead of running nested.

 - Add CONFIG_USERFAULTFD to the KVM selftests config fragment in the
   interest of CI systems.

 - Avoid VM-wide stop-the-world operations when a vCPU accesses its own
   redistributor.

 - Serialize when toggling CPACR_EL1.SMEN to avoid unexpected exceptions
   in the host.

 - Aesthetic and comment/kerneldoc fixes

 - Drop the vestiges of the old Columbia mailing list and add [Oliver]
   as co-maintainer

This also drags in arm64's 'for-next/sme2' branch, because both it and
the PSCI relay changes touch the EL2 initialization code.
parents 7f604e92 96a4627d

Documentation/admin-guide/kernel-parameters.txt

+6 −1
Original line number Diff line number Diff line
@@ -2553,9 +2553,14 @@ 
			protected: nVHE-based mode with support for guests whose

				   state is kept private from the host.



			nested: VHE-based mode with support for nested

				virtualization. Requires at least ARMv8.3

				hardware.



			Defaults to VHE/nVHE based on hardware support. Setting

			mode to "protected" will disable kexec and hibernation

			for the host.

			for the host. "nested" is experimental and should be

			used with extreme caution.



	kvm-arm.vgic_v3_group0_trap=

			[KVM,ARM] Trap guest accesses to GICv3 group-0

Documentation/arm64/booting.rst

+10 −0
Original line number Diff line number Diff line
@@ -369,6 +369,16 @@ Before jumping into the kernel, the following conditions must be met: 


    - HCR_EL2.ATA (bit 56) must be initialised to 0b1.



  For CPUs with the Scalable Matrix Extension version 2 (FEAT_SME2):



  - If EL3 is present:



    - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1.



 - If the kernel is entered at EL1 and EL2 is present:



    - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.



The requirements described above for CPU mode, caches, MMUs, architected

timers, coherency and system registers apply to all CPUs.  All CPUs must

enter the kernel in the same exception level.  Where the values documented

Documentation/arm64/elf_hwcaps.rst

+18 −0
Original line number Diff line number Diff line
@@ -284,6 +284,24 @@ HWCAP2_RPRFM 
HWCAP2_SVE2P1

    Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0010.



HWCAP2_SME2

    Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0001.



HWCAP2_SME2P1

    Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0010.



HWCAP2_SMEI16I32

    Functionality implied by ID_AA64SMFR0_EL1.I16I32 == 0b0101



HWCAP2_SMEBI32I32

    Functionality implied by ID_AA64SMFR0_EL1.BI32I32 == 0b1



HWCAP2_SMEB16B16

    Functionality implied by ID_AA64SMFR0_EL1.B16B16 == 0b1



HWCAP2_SMEF16F16

    Functionality implied by ID_AA64SMFR0_EL1.F16F16 == 0b1



4. Unused AT_HWCAP bits

-----------------------

Documentation/arm64/sme.rst

+43 −9
Original line number Diff line number Diff line
@@ -18,14 +18,19 @@ model features for SME is included in Appendix A. 
1.  General

-----------



* PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA

  register state and TPIDR2_EL0 are tracked per thread.

* PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA and (when

  present) ZTn register state and TPIDR2_EL0 are tracked per thread.



* The presence of SME is reported to userspace via HWCAP2_SME in the aux vector

  AT_HWCAP2 entry.  Presence of this flag implies the presence of the SME

  instructions and registers, and the Linux-specific system interfaces

  described in this document.  SME is reported in /proc/cpuinfo as "sme".



* The presence of SME2 is reported to userspace via HWCAP2_SME2 in the

  aux vector AT_HWCAP2 entry.  Presence of this flag implies the presence of

  the SME2 instructions and ZT0, and the Linux-specific system interfaces

  described in this document.  SME2 is reported in /proc/cpuinfo as "sme2".



* Support for the execution of SME instructions in userspace can also be

  detected by reading the CPU ID register ID_AA64PFR1_EL1 using an MRS

  instruction, and checking that the value of the SME field is nonzero. [3]
@@ -44,6 +49,7 @@ model features for SME is included in Appendix A. 
	HWCAP2_SME_B16F32

	HWCAP2_SME_F32F32

	HWCAP2_SME_FA64

        HWCAP2_SME2



  This list may be extended over time as the SME architecture evolves.
@@ -52,8 +58,8 @@ model features for SME is included in Appendix A. 
  cpu-feature-registers.txt for details.



* Debuggers should restrict themselves to interacting with the target via the

  NT_ARM_SVE, NT_ARM_SSVE and NT_ARM_ZA regsets.  The recommended way

  of detecting support for these regsets is to connect to a target process

  NT_ARM_SVE, NT_ARM_SSVE, NT_ARM_ZA and NT_ARM_ZT regsets.  The recommended

  way of detecting support for these regsets is to connect to a target process

  first and then attempt a



	ptrace(PTRACE_GETREGSET, pid, NT_ARM_<regset>, &iov).
@@ -89,13 +95,13 @@ be zeroed. 
-------------------------



* On syscall PSTATE.ZA is preserved, if PSTATE.ZA==1 then the contents of the

  ZA matrix are preserved.

  ZA matrix and ZTn (if present) are preserved.



* On syscall PSTATE.SM will be cleared and the SVE registers will be handled

  as per the standard SVE ABI.



* Neither the SVE registers nor ZA are used to pass arguments to or receive

  results from any syscall.

* None of the SVE registers, ZA or ZTn are used to pass arguments to

  or receive results from any syscall.



* On process creation (eg, clone()) the newly created process will have

  PSTATE.SM cleared.
@@ -134,6 +140,14 @@ be zeroed. 
  __reserved[] referencing this space.  za_context is then written in the

  extra space.  Refer to [1] for further details about this mechanism.



* If ZTn is supported and PSTATE.ZA==1 then a signal frame record for ZTn will

  be generated.



* The signal record for ZTn has magic ZT_MAGIC (0x5a544e01) and consists of a

  standard signal frame header followed by a struct zt_context specifying

  the number of ZTn registers supported by the system, then zt_context.nregs

  blocks of 64 bytes of data per register.





5.  Signal return

-----------------
@@ -151,6 +165,9 @@ When returning from a signal handler: 
  the signal frame does not match the current vector length, the signal return

  attempt is treated as illegal, resulting in a forced SIGSEGV.



* If ZTn is not supported or PSTATE.ZA==0 then it is illegal to have a

  signal frame record for ZTn, resulting in a forced SIGSEGV.





6.  prctl extensions

--------------------
@@ -214,8 +231,8 @@ prctl(PR_SME_SET_VL, unsigned long arg) 
      vector length that will be applied at the next execve() by the calling

      thread.



    * Changing the vector length causes all of ZA, P0..P15, FFR and all bits of

      Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become

    * Changing the vector length causes all of ZA, ZTn, P0..P15, FFR and all

      bits of Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become

      unspecified, including both streaming and non-streaming SVE state.

      Calling PR_SME_SET_VL with vl equal to the thread's current vector

      length, or calling PR_SME_SET_VL with the PR_SVE_SET_VL_ONEXEC flag,
@@ -317,6 +334,15 @@ The regset data starts with struct user_za_header, containing: 


* The effect of writing a partial, incomplete payload is unspecified.



* A new regset NT_ARM_ZT is defined for access to ZTn state via

  PTRACE_GETREGSET and PTRACE_SETREGSET.



* The NT_ARM_ZT regset consists of a single 512 bit register.



* When PSTATE.ZA==0 reads of NT_ARM_ZT will report all bits of ZTn as 0.



* Writes to NT_ARM_ZT will set PSTATE.ZA to 1.





8.  ELF coredump extensions

---------------------------
@@ -331,6 +357,11 @@ The regset data starts with struct user_za_header, containing: 
  been read if a PTRACE_GETREGSET of NT_ARM_ZA were executed for each thread

  when the coredump was generated.



* A NT_ARM_ZT note will be added to each coredump for each thread of the

  dumped process.  The contents will be equivalent to the data that would have

  been read if a PTRACE_GETREGSET of NT_ARM_ZT were executed for each thread

  when the coredump was generated.



* The NT_ARM_TLS note will be extended to two registers, the second register

  will contain TPIDR2_EL0 on systems that support SME and will be read as

  zero with writes ignored otherwise.
@@ -406,6 +437,9 @@ In A64 state, SME adds the following: 
  For best system performance it is strongly encouraged for software to enable

  ZA only when it is actively being used.



* A new ZT0 register is introduced when SME2 is present. This is a 512 bit

  register which is accessible when PSTATE.ZA is set, as ZA itself is.



* Two new 1 bit fields in PSTATE which may be controlled via the SMSTART and

  SMSTOP instructions or by access to the SVCR system register:

MAINTAINERS

+1 −2
Original line number Diff line number Diff line
@@ -11362,13 +11362,12 @@ F: virt/kvm/* 








KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64)









M:	Marc Zyngier <maz@kernel.org>









M:	Oliver Upton <oliver.upton@linux.dev>









R:	James Morse <james.morse@arm.com>









R:	Suzuki K Poulose <suzuki.poulose@arm.com>









R:	Oliver Upton <oliver.upton@linux.dev>









R:	Zenghui Yu <yuzenghui@huawei.com>









L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)









L:	kvmarm@lists.linux.dev









L:	kvmarm@lists.cs.columbia.edu (deprecated, moderated for non-subscribers)









S:	Maintained









T:	git git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git









F:	arch/arm64/include/asm/kvm*