Commit 407d0c2c authored by Faiz Abbas's avatar Faiz Abbas Committed by Ulf Hansson
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dt-bindings: mmc: sdhci-am654: Convert sdhci-am654 controller documentation to json schema 



Convert sdhci-am654 documentation to yaml format. The new file
sdhci-am654.yaml will inherit from mmc-controller.yaml.

Signed-off-by: default avatarFaiz Abbas <faiz_abbas@ti.com>
Link: https://lore.kernel.org/r/20200923105206.7988-2-faiz_abbas@ti.com


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 975520fc

Documentation/devicetree/bindings/mmc/sdhci-am654.txt

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Device Tree Bindings for the SDHCI Controllers present on TI's AM654 SOCs



The bindings follow the mmc[1], clock[2] and interrupt[3] bindings.

Only deviations are documented here.



  [1] Documentation/devicetree/bindings/mmc/mmc.txt

  [2] Documentation/devicetree/bindings/clock/clock-bindings.txt

  [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt



Required Properties:

	- compatible: should be one of:

			"ti,am654-sdhci-5.1": SDHCI on AM654 device.

			"ti,j721e-sdhci-8bit": 8 bit SDHCI on J721E device.

			"ti,j721e-sdhci-4bit": 4 bit SDHCI on J721E device.

			"ti,j7200-sdhci-8bit": 8 bit SDHCI on J7200 device.

			"ti,j7200-sdhci-4bit": 4 bit SDHCI on J7200 device.

	- reg: Must be two entries.

		- The first should be the sdhci register space

		- The second should the subsystem/phy register space

	- clocks: Handles to the clock inputs.

	- clock-names: Tuple including "clk_xin" and "clk_ahb"

	- interrupts: Interrupt specifiers

	Output tap delay for each speed mode:

	- ti,otap-del-sel-legacy

	- ti,otap-del-sel-mmc-hs

	- ti,otap-del-sel-sd-hs

	- ti,otap-del-sel-sdr12

	- ti,otap-del-sel-sdr25

	- ti,otap-del-sel-sdr50

	- ti,otap-del-sel-sdr104

	- ti,otap-del-sel-ddr50

	- ti,otap-del-sel-ddr52

	- ti,otap-del-sel-hs200

	- ti,otap-del-sel-hs400

	  These bindings must be provided otherwise the driver will disable the

	  corresponding speed mode (i.e. all nodes must provide at least -legacy)



Optional Properties (Required for ti,am654-sdhci-5.1,

				  ti,j721e-sdhci-8bit,

				  ti,j7200-sdhci-8bit):

	- ti,trm-icp: DLL trim select

	- ti,driver-strength-ohm: driver strength in ohms.

				  Valid values are 33, 40, 50, 66 and 100 ohms.

Optional Properties:

	- ti,strobe-sel: strobe select delay for HS400 speed mode. Default value: 0x0.

	- ti,clkbuf-sel: Clock Delay Buffer Select



Example:



	sdhci0: sdhci@4f80000 {

		compatible = "ti,am654-sdhci-5.1";

		reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;

		power-domains = <&k3_pds 47>;

		clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;

		clock-names = "clk_ahb", "clk_xin";

		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;

		sdhci-caps-mask = <0x80000007 0x0>;

		mmc-ddr-1_8v;

		ti,otap-del-sel-legacy = <0x0>;

		ti,otap-del-sel-mmc-hs = <0x0>;

		ti,otap-del-sel-ddr52 = <0x5>;

		ti,otap-del-sel-hs200 = <0x5>;

		ti,otap-del-sel-hs400 = <0x0>;

		ti,trm-icp = <0x8>;

	};

Documentation/devicetree/bindings/mmc/sdhci-am654.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/

%YAML 1.2

---

$id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"

$schema : "http://devicetree.org/meta-schemas/core.yaml#"



title: TI AM654 MMC Controller



maintainers:

  - Ulf Hansson <ulf.hansson@linaro.org>



allOf:

  - $ref: mmc-controller.yaml#



properties:

  compatible:

    enum:

      - ti,am654-sdhci-5.1

      - ti,j721e-sdhci-8bit

      - ti,j721e-sdhci-4bit

      - ti,j7200-sdhci-8bit

      - ti,j721e-sdhci-4bit



  reg:

    maxItems: 2



  interrupts:

    maxItems: 1



  power-domains:

    maxItems: 1



  clocks:

    minItems: 1

    maxItems: 2

    description: Handles to input clocks



  clock-names:

    minItems: 1

    maxItems: 2

    items:

      - const: clk_ahb

      - const: clk_xin



  # PHY output tap delays:

  # Used to delay the data valid window and align it to the sampling clock.

  # Binding needs to be provided for each supported speed mode otherwise the

  # corresponding mode will be disabled.



  ti,otap-del-sel-legacy:

    description: Output tap delay for SD/MMC legacy timing

    $ref: "/schemas/types.yaml#/definitions/uint32"

    minimum: 0

    maximum: 0xf



  ti,otap-del-sel-mmc-hs:

    description: Output tap delay for MMC high speed timing

    $ref: "/schemas/types.yaml#/definitions/uint32"

    minimum: 0

    maximum: 0xf



  ti,otap-del-sel-sd-hs:

    description: Output tap delay for SD high speed timing

    $ref: "/schemas/types.yaml#/definitions/uint32"

    minimum: 0

    maximum: 0xf



  ti,otap-del-sel-sdr12:

    description: Output tap delay for SD UHS SDR12 timing

    $ref: "/schemas/types.yaml#/definitions/uint32"

    minimum: 0

    maximum: 0xf



  ti,otap-del-sel-sdr25:

    description: Output tap delay for SD UHS SDR25 timing

    $ref: "/schemas/types.yaml#/definitions/uint32"

    minimum: 0

    maximum: 0xf



  ti,otap-del-sel-sdr50:

    description: Output tap delay for SD UHS SDR50 timing

    $ref: "/schemas/types.yaml#/definitions/uint32"

    minimum: 0

    maximum: 0xf



  ti,otap-del-sel-sdr104:

    description: Output tap delay for SD UHS SDR104 timing

    $ref: "/schemas/types.yaml#/definitions/uint32"

    minimum: 0

    maximum: 0xf



  ti,otap-del-sel-ddr50:

    description: Output tap delay for SD UHS DDR50 timing

    $ref: "/schemas/types.yaml#/definitions/uint32"

    minimum: 0

    maximum: 0xf



  ti,otap-del-sel-ddr52:

    description: Output tap delay for eMMC DDR52 timing

    $ref: "/schemas/types.yaml#/definitions/uint32"

    minimum: 0

    maximum: 0xf



  ti,otap-del-sel-hs200:

    description: Output tap delay for eMMC HS200 timing

    $ref: "/schemas/types.yaml#/definitions/uint32"

    minimum: 0

    maximum: 0xf



  ti,otap-del-sel-hs400:

    description: Output tap delay for eMMC HS400 timing

    $ref: "/schemas/types.yaml#/definitions/uint32"

    minimum: 0

    maximum: 0xf



  ti,trm-icp:

    description: DLL trim select

    $ref: "/schemas/types.yaml#/definitions/uint32"

    minimum: 0

    maximum: 0xf



  ti,driver-strength-ohm:

    description: DLL drive strength in ohms

    $ref: "/schemas/types.yaml#/definitions/uint32"

    oneOf:

      - enum:

        - 33

        - 40

        - 50

        - 66

        - 100



  ti,strobe-sel:

    description: strobe select delay for HS400 speed mode.

    $ref: "/schemas/types.yaml#/definitions/uint32"



  ti,clkbuf-sel:

    description: Clock Delay Buffer Select

    $ref: "/schemas/types.yaml#/definitions/uint32"



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - ti,otap-del-sel-legacy



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    bus {

        #address-cells = <2>;

        #size-cells = <2>;



        mmc0: mmc@4f80000 {

            compatible = "ti,am654-sdhci-5.1";

            reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;

            power-domains = <&k3_pds 47>;

            clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;

            clock-names = "clk_ahb", "clk_xin";

            interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;

            sdhci-caps-mask = <0x80000007 0x0>;

            mmc-ddr-1_8v;

            ti,otap-del-sel-legacy = <0x0>;

            ti,otap-del-sel-mmc-hs = <0x0>;

            ti,otap-del-sel-ddr52 = <0x5>;

            ti,otap-del-sel-hs200 = <0x5>;

            ti,otap-del-sel-hs400 = <0x0>;

            ti,trm-icp = <0x8>;

        };

    };