Commit 4078aa68 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'ata-6.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/libata 

Pull ata updates from Damien Le Moal:

 - Print the timeout value for internal command failures due to a
   timeout (from Tomas)

 - Improve parameter names in ata_dev_set_feature() to clarify this
   function use (from Niklas)

 - Improve the ahci driver low power mode setting initialization to
   allow more flexibility for the user (from Rafael)

 - Several patches to remove redundant variables in libata-core,
   libata-eh and the pata_macio driver and to fix typos in comments
   (from Jinpeng, Shaomin, Ye)

 - Some code simplifications and macro renaming (for clarity) in various
   functions of libata-core (from me)

 - Add a missing check for a potential failure of sata_scr_read() in
   sata_print_link_status() (from Li)

 - Cleanup of libata Kconfig PATA_PLATFORM and PATA_OF_PLATFORM options
   (from Lukas)

 - Cleanups of ata dt-bindings and improvements of libahci_platform,
   ahci and libahci code (from Serge)

 - New driver for Synopsys AHCI SATA controllers, based of the generic
   ahci code (from Serge). One compilation warning fix is added for this
   driver (from me)

 - Several fixes to macros used to discover a drive capabilities to be
   consistent with the ACS specifications (from Niklas)

 - A couple of simplifcations to some libata functions, removing
   unnecessary arguments (from Niklas)

 - An improvements to libata-eh code to avoid unnecessary link reset
   when revalidating a drive after a failed command. In practice, this
   extra, unneeded reset, reset does not cause any arm beyond slightly
   slowing down error recovery (from Niklas)

* tag 'ata-6.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/libata: (45 commits)
  ata: libata-eh: avoid needless hard reset when revalidating link
  ata: libata: drop superfluous ata_eh_analyze_tf() parameter
  ata: libata: drop superfluous ata_eh_request_sense() parameter
  ata: fix ata_id_has_dipm()
  ata: fix ata_id_has_ncq_autosense()
  ata: fix ata_id_has_devslp()
  ata: fix ata_id_sense_reporting_enabled() and ata_id_has_sense_reporting()
  ata: libata-eh: Remove the unneeded result variable
  ata: ahci_st: Enable compile test
  ata: ahci_st: Fix compilation warning
  MAINTAINERS: Add maintainers for DWC AHCI SATA driver
  ata: ahci-dwc: Add Baikal-T1 AHCI SATA interface support
  ata: ahci-dwc: Add platform-specific quirks support
  dt-bindings: ata: ahci: Add Baikal-T1 AHCI SATA controller DT schema
  ata: ahci: Add DWC AHCI SATA controller support
  ata: libahci_platform: Add function returning a clock-handle by id
  dt-bindings: ata: ahci: Add DWC AHCI SATA controller DT schema
  ata: ahci: Introduce firmware-specific caps initialization
  ata: ahci: Convert __ahci_port_base to accepting hpriv as arguments
  ata: libahci: Don't read AHCI version twice in the save-config method
  ...
parents 9d84bb40 71d7b6e5

Documentation/devicetree/bindings/ata/ahci-common.yaml

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+123 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/ata/ahci-common.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Common Properties for Serial ATA AHCI controllers



maintainers:

  - Hans de Goede <hdegoede@redhat.com>

  - Damien Le Moal <damien.lemoal@opensource.wdc.com>



description:

  This document defines device tree properties for a common AHCI SATA

  controller implementation. It's hardware interface is supposed to

  conform to the technical standard defined by Intel (see Serial ATA

  Advanced Host Controller Interface specification for details). The

  document doesn't constitute a DT-node binding by itself but merely

  defines a set of common properties for the AHCI-compatible devices.



select: false



allOf:

  - $ref: sata-common.yaml#



properties:

  reg:

    description:

      Generic AHCI registers space conforming to the Serial ATA AHCI

      specification.



  reg-names:

    description: CSR space IDs

    contains:

      const: ahci



  interrupts:

    description:

      Generic AHCI state change interrupt. Can be implemented either as a

      single line attached to the controller or as a set of the signals

      indicating the particular port events.

    minItems: 1

    maxItems: 32



  ahci-supply:

    description: Power regulator for AHCI controller



  target-supply:

    description: Power regulator for SATA target device



  phy-supply:

    description: Power regulator for SATA PHY



  phys:

    description: Reference to the SATA PHY node

    maxItems: 1



  phy-names:

    const: sata-phy



  hba-cap:

    $ref: '/schemas/types.yaml#/definitions/uint32'

    description:

      Bitfield of the HBA generic platform capabilities like Staggered

      Spin-up or Mechanical Presence Switch support. It can be used to

      appropriately initialize the HWinit fields of the HBA CAP register

      in case if the system firmware hasn't done it.



  ports-implemented:

    $ref: '/schemas/types.yaml#/definitions/uint32'

    description:

      Mask that indicates which ports the HBA supports. Useful if PI is not

      programmed by the BIOS, which is true for some embedded SoC's.



patternProperties:

  "^sata-port@[0-9a-f]+$":

    $ref: '#/$defs/ahci-port'

    description:

      It is optionally possible to describe the ports as sub-nodes so

      to enable each port independently when dealing with multiple PHYs.



required:

  - reg

  - interrupts



additionalProperties: true



$defs:

  ahci-port:

    $ref: /schemas/ata/sata-common.yaml#/$defs/sata-port



    properties:

      reg:

        description:

          AHCI SATA port identifier. By design AHCI controller can't have

          more than 32 ports due to the CAP.NP fields and PI register size

          constraints.

        minimum: 0

        maximum: 31



      phys:

        description: Individual AHCI SATA port PHY

        maxItems: 1



      phy-names:

        description: AHCI SATA port PHY ID

        const: sata-phy



      target-supply:

        description: Power regulator for SATA port target device



      hba-port-cap:

        $ref: '/schemas/types.yaml#/definitions/uint32'

        description:

          Bitfield of the HBA port-specific platform capabilities like Hot

          plugging, eSATA, FIS-based Switching, etc (see AHCI specification

          for details). It can be used to initialize the HWinit fields of

          the PxCMD register in case if the system firmware hasn't done it.



    required:

      - reg



...

Documentation/devicetree/bindings/ata/ahci-platform.yaml

+19 −73
Original line number Diff line number Diff line
@@ -30,14 +30,11 @@ select: 
          - marvell,armada-3700-ahci

          - marvell,armada-8k-ahci

          - marvell,berlin2q-ahci

          - snps,dwc-ahci

          - snps,spear-ahci

  required:

    - compatible



allOf:

  - $ref: "sata-common.yaml#"



  - $ref: "ahci-common.yaml#"



properties:

  compatible:
@@ -49,17 +46,11 @@ properties: 
              - marvell,berlin2-ahci

              - marvell,berlin2q-ahci

          - const: generic-ahci

      - items:

          - enum:

              - rockchip,rk3568-dwc-ahci

          - const: snps,dwc-ahci

      - enum:

          - cavium,octeon-7130-ahci

          - hisilicon,hisi-ahci

          - ibm,476gtr-ahci

          - marvell,armada-3700-ahci

          - snps,dwc-ahci

          - snps,spear-ahci



  reg:

    minItems: 1
@@ -69,91 +60,36 @@ properties: 
    maxItems: 1



  clocks:

    description:

      Clock IDs array as required by the controller.

    minItems: 1

    maxItems: 3



  clock-names:

    description:

      Names of clocks corresponding to IDs in the clock property.

    minItems: 1

    maxItems: 3



  interrupts:

    maxItems: 1



  ahci-supply:

    description:

      regulator for AHCI controller



  dma-coherent: true



  phy-supply:

    description:

      regulator for PHY power



  phys:

    description:

      List of all PHYs on this controller

    maxItems: 1



  phy-names:

    description:

      Name specifier for the PHYs

    maxItems: 1



  ports-implemented:

    $ref: '/schemas/types.yaml#/definitions/uint32'

    description: |

      Mask that indicates which ports that the HBA supports

      are available for software to use. Useful if PORTS_IMPL

      is not programmed by the BIOS, which is true with

      some embedded SoCs.

    maximum: 0x1f



  power-domains:

    maxItems: 1



  resets:

    maxItems: 1



  target-supply:

    description:

      regulator for SATA target power



required:

  - compatible

  - reg

  - interrupts



patternProperties:

  "^sata-port@[0-9a-f]+$":

    type: object

    additionalProperties: false

    description:

      Subnode with configuration of the Ports.

    $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port



    properties:

      reg:

        maxItems: 1



      phys:

        maxItems: 1



      phy-names:

        maxItems: 1

    anyOf:

      - required: [ phys ]

      - required: [ target-supply ]



      target-supply:

        description:

          regulator for SATA target power

    unevaluatedProperties: false



required:

  - compatible

  - reg



    anyOf:

      - required: [ phys ]

      - required: [ target-supply ]

  - interrupts



unevaluatedProperties: false
@@ -167,6 +103,8 @@ examples: 
  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/berlin2q.h>

    #include <dt-bindings/ata/ahci.h>



    sata@f7e90000 {

        compatible = "marvell,berlin2q-ahci", "generic-ahci";

        reg = <0xf7e90000 0x1000>;
@@ -175,15 +113,23 @@ examples: 
        #address-cells = <1>;

        #size-cells = <0>;



        hba-cap = <HBA_SMPS>;



        sata0: sata-port@0 {

            reg = <0>;



            phys = <&sata_phy 0>;

            target-supply = <&reg_sata0>;



            hba-port-cap = <(HBA_PORT_FBSCP | HBA_PORT_ESP)>;

        };



        sata1: sata-port@1 {

            reg = <1>;



            phys = <&sata_phy 1>;

            target-supply = <&reg_sata1>;



            hba-port-cap = <(HBA_PORT_HPCP | HBA_PORT_MPSP | HBA_PORT_FBSCP)>;

        };

    };

Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Baikal-T1 SoC AHCI SATA controller



maintainers:

  - Serge Semin <fancer.lancer@gmail.com>



description:

  AHCI SATA controller embedded into the Baikal-T1 SoC is based on the

  DWC AHCI SATA v4.10a IP-core.



allOf:

  - $ref: snps,dwc-ahci-common.yaml#



properties:

  compatible:

    const: baikal,bt1-ahci



  clocks:

    items:

      - description: Peripheral APB bus clock

      - description: Application AXI BIU clock

      - description: SATA Ports reference clock



  clock-names:

    items:

      - const: pclk

      - const: aclk

      - const: ref



  resets:

    items:

      - description: Application AXI BIU domain reset

      - description: SATA Ports clock domain reset



  reset-names:

    items:

      - const: arst

      - const: ref



  ports-implemented:

    maximum: 0x3



patternProperties:

  "^sata-port@[0-1]$":

    $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port



    properties:

      reg:

        minimum: 0

        maximum: 1



      snps,tx-ts-max:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Due to having AXI3 bus interface utilized the maximum Tx DMA

          transaction size can't exceed 16 beats (AxLEN[3:0]).

        enum: [ 1, 2, 4, 8, 16 ]



      snps,rx-ts-max:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Due to having AXI3 bus interface utilized the maximum Rx DMA

          transaction size can't exceed 16 beats (AxLEN[3:0]).

        enum: [ 1, 2, 4, 8, 16 ]



    unevaluatedProperties: false



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - resets



unevaluatedProperties: false



examples:

  - |

    sata@1f050000 {

      compatible = "baikal,bt1-ahci";

      reg = <0x1f050000 0x2000>;

      #address-cells = <1>;

      #size-cells = <0>;



      interrupts = <0 64 4>;



      clocks = <&ccu_sys 1>, <&ccu_axi 2>, <&sata_ref_clk>;

      clock-names = "pclk", "aclk", "ref";



      resets = <&ccu_axi 2>, <&ccu_sys 0>;

      reset-names = "arst", "ref";



      ports-implemented = <0x3>;



      sata-port@0 {

        reg = <0>;



        snps,tx-ts-max = <4>;

        snps,rx-ts-max = <4>;

      };



      sata-port@1 {

        reg = <1>;



        snps,tx-ts-max = <4>;

        snps,rx-ts-max = <4>;

      };

    };

...

Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml

+1 −3
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ maintainers: 
  - Florian Fainelli <f.fainelli@gmail.com>



allOf:

  - $ref: sata-common.yaml#

  - $ref: ahci-common.yaml#



properties:

  compatible:
@@ -41,8 +41,6 @@ properties: 
  interrupts:

    maxItems: 1



  dma-coherent: true



if:

  properties:

    compatible:

Documentation/devicetree/bindings/ata/sata-common.yaml

+11 −6
Original line number Diff line number Diff line
@@ -31,22 +31,27 @@ properties: 
  "#size-cells":

    const: 0



  dma-coherent: true



patternProperties:

  "^sata-port@[0-9a-e]$":

    $ref: '#/$defs/sata-port'

    description: |

      DT nodes for ports connected on the SATA host. The SATA port

      nodes will be named "sata-port".



additionalProperties: true



$defs:

  sata-port:

    type: object



    properties:

      reg:

        minimum: 0

        maximum: 14

        description:

          The ID number of the drive port SATA can potentially use a port

          multiplier making it possible to connect up to 15 disks to a single

          SATA port.



additionalProperties: true

          The ID number of the SATA port. Aside with being directly used,

          each port can have a Port Multiplier attached thus allowing to

          access more than one drive by means of a single SATA port.



...