Unverified Commit 40450653 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!13151 [OLK-6.6] arm64: errata: Unify and expand speculative SSBS workaround 

Merge Pull Request from: @justinhe2 
 
Expand the speculative SSBS workaround to more CPUs, e.g. Neoverse-N3
All the 5 patches came from upstream、
arm64: errata: Expand speculative SSBS workaround once more
arm64: errata: Expand speculative SSBS workaround (again)
arm64: errata: Expand speculative SSBS workaround
arm64: errata: Unify speculative SSBS errata logic
arm64: errata: Add workaround for Arm errata 3194386 and 3312417

https://gitee.com/openeuler/kernel/issues/IB3K2H 
 
Link:https://gitee.com/openeuler/kernel/pulls/13151

 

Reviewed-by: default avatarZhang Jianhua <chris.zjh@huawei.com>
Signed-off-by: default avatarZhang Peng <zhangpeng362@huawei.com>
parents b84dc01b 483a458a

Documentation/arch/arm64/silicon-errata.rst

+42 −0
Original line number Diff line number Diff line
@@ -121,32 +121,72 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A76      | #1463225        | ARM64_ERRATUM_1463225       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A76      | #3324349        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A77      | #1508412        | ARM64_ERRATUM_1508412       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A77      | #3324348        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A78      | #3324344        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A78C     | #3324346,3324347| ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2054223        | ARM64_ERRATUM_2054223       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2224489        | ARM64_ERRATUM_2224489       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #3324338        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A715     | #2645198        | ARM64_ERRATUM_2645198       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A715     | #3456084        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A720     | #3456091        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A725     | #3456106        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X1       | #3324344        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X1C      | #3324346        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2224489        | ARM64_ERRATUM_2224489       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #3324338        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X3       | #3324335        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X4       | #3194386        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X925     | #3324334        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1349291        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1542419        | ARM64_ERRATUM_1542419       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #3324349        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2139208        | ARM64_ERRATUM_2139208       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2067961        | ARM64_ERRATUM_2067961       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2253138        | ARM64_ERRATUM_2253138       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #3324339        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N3     | #3456111        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V1     | #3324341        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V2     | #3324336        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | MMU-500         | #841119,826419  | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | MMU-600         | #1076982,1209401| N/A                         |
@@ -256,3 +296,5 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Microsoft      | Azure Cobalt 100| #2253138        | ARM64_ERRATUM_2253138       |

+----------------+-----------------+-----------------+-----------------------------+

| Microsoft      | Azure Cobalt 100| #3324339        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+40 −0
Original line number Diff line number Diff line
@@ -1081,6 +1081,46 @@ config ARM64_ERRATUM_3117295 


	  If unsure, say Y.



config ARM64_ERRATUM_3194386

	bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"

	default y

	help

	  This option adds the workaround for the following errata:



	  * ARM Cortex-A76 erratum 3324349

	  * ARM Cortex-A77 erratum 3324348

	  * ARM Cortex-A78 erratum 3324344

	  * ARM Cortex-A78C erratum 3324346

	  * ARM Cortex-A78C erratum 3324347

	  * ARM Cortex-A710 erratam 3324338

	  * ARM Cortex-A715 errartum 3456084

	  * ARM Cortex-A720 erratum 3456091

	  * ARM Cortex-A725 erratum 3456106

	  * ARM Cortex-X1 erratum 3324344

	  * ARM Cortex-X1C erratum 3324346

	  * ARM Cortex-X2 erratum 3324338

	  * ARM Cortex-X3 erratum 3324335

	  * ARM Cortex-X4 erratum 3194386

	  * ARM Cortex-X925 erratum 3324334

	  * ARM Neoverse-N1 erratum 3324349

	  * ARM Neoverse N2 erratum 3324339

	  * ARM Neoverse-N3 erratum 3456111

	  * ARM Neoverse-V1 erratum 3324341

	  * ARM Neoverse V2 erratum 3324336

	  * ARM Neoverse-V3 erratum 3312417



	  On affected cores "MSR SSBS, #0" instructions may not affect

	  subsequent speculative instructions, which may permit unexepected

	  speculative store bypassing.



	  Work around this problem by placing a Speculation Barrier (SB) or

	  Instruction Synchronization Barrier (ISB) after kernel changes to

	  SSBS. The presence of the SSBS special-purpose register is hidden

	  from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace

	  will use the PR_SPEC_STORE_BYPASS prctl to change SSBS.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/configs/openeuler_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -425,6 +425,7 @@ CONFIG_ARM64_ERRATUM_2645198=y 
CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y

CONFIG_ARM64_ERRATUM_2966298=y

CONFIG_ARM64_ERRATUM_3117295=y

CONFIG_ARM64_ERRATUM_3194386=y

CONFIG_CAVIUM_ERRATUM_22375=y

CONFIG_CAVIUM_ERRATUM_23144=y

CONFIG_CAVIUM_ERRATUM_23154=y

arch/arm64/kernel/cpu_errata.c

+34 −0
Original line number Diff line number Diff line
@@ -534,6 +534,33 @@ static const struct midr_range erratum_ac03_cpu_38_list[] = { 
};

#endif



#ifdef CONFIG_ARM64_ERRATUM_3194386

static const struct midr_range erratum_spec_ssbs_list[] = {

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),

	MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),

	{}

};

#endif



const struct arm64_cpu_capabilities arm64_errata[] = {

#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE

	{
@@ -848,6 +875,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.cpu_enable = cpu_clear_bf16_from_user_emulation,

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_3194386

	{

		.desc = "SSBS not fully self-synchronizing",

		.capability = ARM64_WORKAROUND_SPECULATIVE_SSBS,

		ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list),

	},

#endif

#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD

	{

		.desc = "ARM errata 2966298, 3117295",

arch/arm64/kernel/cpufeature.c

+12 −0
Original line number Diff line number Diff line
@@ -2260,6 +2260,17 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 
}

#endif /* CONFIG_ARM64_MTE */



static void user_feature_fixup(void)

{

	if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) {

		struct arm64_ftr_reg *regp;



		regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1);

		if (regp)

			regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK;

	}

}



static void elf_hwcap_fixup(void)

{

#ifdef CONFIG_ARM64_ERRATUM_1742098
@@ -3587,6 +3598,7 @@ void __init setup_cpu_features(void) 
	u32 cwg;



	setup_system_capabilities();

	user_feature_fixup();

	setup_elf_hwcaps(arm64_elf_hwcaps);



	if (system_supports_32bit_el0()) {