Commit 40379a00 authored by Leon Romanovsky's avatar Leon Romanovsky
Browse files

net/mlx5_fpga: Drop INNOVA TLS support 

Mellanox INNOVA TLS cards are EOL in May, 2018 [1]. As such, the code
is unmaintained, untested and not in-use by any upstream/distro oriented
customers. In order to reduce code complexity, drop the kernel code.

[1] https://network.nvidia.com/related-docs/eol/LCR-000286.pdf

Link: https://lore.kernel.org/r/b88add368def721ea9d054cb69def72d9e3f67aa.1649073691.git.leonro@nvidia.com


Reviewed-by: default avatarTariq Toukan <tariqt@nvidia.com>
Reviewed-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
Signed-off-by: default avatarLeon Romanovsky <leonro@nvidia.com>
parent 31231092

drivers/net/ethernet/mellanox/mlx5/core/Kconfig

+0 −14
Original line number Diff line number Diff line
@@ -177,20 +177,6 @@ config MLX5_EN_IPSEC 
	  Note: Support for hardware with this capability needs to be selected

	  for this option to become available.



config MLX5_FPGA_TLS

	bool "Mellanox Technologies TLS Innova support"

	depends on TLS_DEVICE

	depends on TLS=y || MLX5_CORE=m

	depends on MLX5_CORE_EN

	depends on MLX5_FPGA

	select MLX5_EN_TLS

	help

	Build TLS support for the Innova family of network cards by Mellanox

	Technologies. Innova network cards are comprised of a ConnectX chip

	and an FPGA chip on one board. If you select this option, the

	mlx5_core driver will include the Innova FPGA core and allow building

	sandbox-specific client drivers.



config MLX5_TLS

	bool "Mellanox Technologies TLS Connect-X support"

	depends on TLS_DEVICE

drivers/net/ethernet/mellanox/mlx5/core/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -90,7 +90,6 @@ mlx5_core-$(CONFIG_MLX5_CORE_IPOIB) += ipoib/ipoib.o ipoib/ethtool.o ipoib/ipoib 
#

mlx5_core-$(CONFIG_MLX5_IPSEC) += accel/ipsec_offload.o

mlx5_core-$(CONFIG_MLX5_FPGA_IPSEC) += fpga/ipsec.o

mlx5_core-$(CONFIG_MLX5_FPGA_TLS)   += fpga/tls.o

mlx5_core-$(CONFIG_MLX5_ACCEL)      += lib/crypto.o accel/tls.o accel/ipsec.o



mlx5_core-$(CONFIG_MLX5_FPGA) += fpga/cmd.o fpga/core.o fpga/conn.o fpga/sdk.o

drivers/net/ethernet/mellanox/mlx5/core/accel/tls.c

+0 −47
Original line number Diff line number Diff line
@@ -37,53 +37,6 @@ 
#include "mlx5_core.h"

#include "lib/mlx5.h"



#ifdef CONFIG_MLX5_FPGA_TLS

#include "fpga/tls.h"



int mlx5_accel_tls_add_flow(struct mlx5_core_dev *mdev, void *flow,

			    struct tls_crypto_info *crypto_info,

			    u32 start_offload_tcp_sn, u32 *p_swid,

			    bool direction_sx)

{

	return mlx5_fpga_tls_add_flow(mdev, flow, crypto_info,

				      start_offload_tcp_sn, p_swid,

				      direction_sx);

}



void mlx5_accel_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,

			     bool direction_sx)

{

	mlx5_fpga_tls_del_flow(mdev, swid, GFP_KERNEL, direction_sx);

}



int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, __be32 handle,

			     u32 seq, __be64 rcd_sn)

{

	return mlx5_fpga_tls_resync_rx(mdev, handle, seq, rcd_sn);

}



bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev)

{

	return mlx5_fpga_is_tls_device(mdev) ||

		mlx5_accel_is_ktls_device(mdev);

}



u32 mlx5_accel_tls_device_caps(struct mlx5_core_dev *mdev)

{

	return mlx5_fpga_tls_device_caps(mdev);

}



int mlx5_accel_tls_init(struct mlx5_core_dev *mdev)

{

	return mlx5_fpga_tls_init(mdev);

}



void mlx5_accel_tls_cleanup(struct mlx5_core_dev *mdev)

{

	mlx5_fpga_tls_cleanup(mdev);

}

#endif



#ifdef CONFIG_MLX5_TLS

int mlx5_ktls_create_key(struct mlx5_core_dev *mdev,

			 struct tls_crypto_info *crypto_info,

drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h

+0 −56
Original line number Diff line number Diff line
@@ -97,60 +97,4 @@ static inline bool 
mlx5e_ktls_type_check(struct mlx5_core_dev *mdev,

		      struct tls_crypto_info *crypto_info) { return false; }

#endif



enum {

	MLX5_ACCEL_TLS_TX = BIT(0),

	MLX5_ACCEL_TLS_RX = BIT(1),

	MLX5_ACCEL_TLS_V12 = BIT(2),

	MLX5_ACCEL_TLS_V13 = BIT(3),

	MLX5_ACCEL_TLS_LRO = BIT(4),

	MLX5_ACCEL_TLS_IPV6 = BIT(5),

	MLX5_ACCEL_TLS_AES_GCM128 = BIT(30),

	MLX5_ACCEL_TLS_AES_GCM256 = BIT(31),

};



struct mlx5_ifc_tls_flow_bits {

	u8         src_port[0x10];

	u8         dst_port[0x10];

	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;

	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;

	u8         ipv6[0x1];

	u8         direction_sx[0x1];

	u8         reserved_at_2[0x1e];

};



#ifdef CONFIG_MLX5_FPGA_TLS

int mlx5_accel_tls_add_flow(struct mlx5_core_dev *mdev, void *flow,

			    struct tls_crypto_info *crypto_info,

			    u32 start_offload_tcp_sn, u32 *p_swid,

			    bool direction_sx);

void mlx5_accel_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,

			     bool direction_sx);

int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, __be32 handle,

			     u32 seq, __be64 rcd_sn);

bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev);

u32 mlx5_accel_tls_device_caps(struct mlx5_core_dev *mdev);

int mlx5_accel_tls_init(struct mlx5_core_dev *mdev);

void mlx5_accel_tls_cleanup(struct mlx5_core_dev *mdev);



#else



static inline int

mlx5_accel_tls_add_flow(struct mlx5_core_dev *mdev, void *flow,

			struct tls_crypto_info *crypto_info,

			u32 start_offload_tcp_sn, u32 *p_swid,

			bool direction_sx) { return -ENOTSUPP; }

static inline void mlx5_accel_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,

					   bool direction_sx) { }

static inline int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, __be32 handle,

					   u32 seq, __be64 rcd_sn) { return 0; }

static inline bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev)

{

	return mlx5_accel_is_ktls_device(mdev);

}

static inline u32 mlx5_accel_tls_device_caps(struct mlx5_core_dev *mdev) { return 0; }

static inline int mlx5_accel_tls_init(struct mlx5_core_dev *mdev) { return 0; }

static inline void mlx5_accel_tls_cleanup(struct mlx5_core_dev *mdev) { }

#endif



#endif	/* __MLX5_ACCEL_TLS_H__ */

drivers/net/ethernet/mellanox/mlx5/core/en.h

+0 −1
Original line number Diff line number Diff line
@@ -354,7 +354,6 @@ enum { 
	MLX5E_RQ_STATE_AM,

	MLX5E_RQ_STATE_NO_CSUM_COMPLETE,

	MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */

	MLX5E_RQ_STATE_FPGA_TLS, /* FPGA TLS enabled */

	MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */

	MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */

};