Commit 4005809b authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: add support to configure MALL for sienna_cichlid (v2) 



Enable Memory Access at Last Level (MALL) feature for sienna_cichlid.

v2: drop module option.  We need to add UAPI so userspace can
request MALL per buffer.

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d0279204

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

+3 −0
Original line number Diff line number Diff line
@@ -76,6 +76,9 @@ struct amdgpu_bo_list_entry; 
/* PTE is handled as PDE for VEGA10 (Translate Further) */

#define AMDGPU_PTE_TF		(1ULL << 56)



/* MALL noalloc for sienna_cichlid, reserved for older ASICs  */

#define AMDGPU_PTE_NOALLOC	(1ULL << 58)



/* PDE Block Fragment Size for VEGA10 */

#define AMDGPU_PDE_BFS(a)	((uint64_t)a << 59)

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

+2 −1
Original line number Diff line number Diff line
@@ -486,7 +486,8 @@ static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid 
/*

 * PTE format on NAVI 10:

 * 63:59 reserved

 * 58:57 reserved

 * 58 reserved and for sienna_cichlid is used for MALL noalloc

 * 57 reserved

 * 56 F

 * 55 L

 * 54 reserved

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

+1 −1
Original line number Diff line number Diff line
@@ -707,7 +707,7 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) 
		temp &= 0xFF0FFF;

		temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |

			 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |

			 0x01000000);

			 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);

		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);



		if (!amdgpu_sriov_vf(adev)) {