Commit 3faf1ce7 authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Wen Zhiwei
Browse files

watchdog: rzg2l_wdt: Rely on the reset driver for doing proper reset 

stable inclusion
from stable-v6.6.70
commit e145b77fb5c1829bfd320f839bfea006a5878b0a
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IBOHV1

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=e145b77fb5c1829bfd320f839bfea006a5878b0a



--------------------------------

[ Upstream commit d8997ed79ed7c7c32b2ae571e0d99a58bbfd01fe ]

The reset driver has been adapted in commit da235d2fac21
("clk: renesas: rzg2l: Check reset monitor registers") to check the reset
monitor bits before declaring reset asserts/de-asserts as
successful/failure operations. With that, there is no need to keep the
reset workaround for RZ/V2M in place in the watchdog driver.

Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: default avatarGuenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20240531065723.1085423-8-claudiu.beznea.uj@bp.renesas.com


Signed-off-by: default avatarGuenter Roeck <linux@roeck-us.net>
Signed-off-by: default avatarWim Van Sebroeck <wim@linux-watchdog.org>
Stable-dep-of: bad201b2ac4e ("watchdog: rzg2l_wdt: Power on the watchdog domain in the restart handler")
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
Signed-off-by: default avatarWen Zhiwei <wenzhiwei@kylinos.cn>
parent e6a361b5

drivers/watchdog/rzg2l_wdt.c

+4 −35
Original line number Diff line number Diff line
@@ -8,7 +8,6 @@ 
#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/io.h>

#include <linux/iopoll.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/of.h>
@@ -54,35 +53,11 @@ struct rzg2l_wdt_priv { 
	struct reset_control *rstc;

	unsigned long osc_clk_rate;

	unsigned long delay;

	unsigned long minimum_assertion_period;

	struct clk *pclk;

	struct clk *osc_clk;

	enum rz_wdt_type devtype;

};



static int rzg2l_wdt_reset(struct rzg2l_wdt_priv *priv)

{

	int err, status;



	if (priv->devtype == WDT_RZV2M) {

		/* WDT needs TYPE-B reset control */

		err = reset_control_assert(priv->rstc);

		if (err)

			return err;

		ndelay(priv->minimum_assertion_period);

		err = reset_control_deassert(priv->rstc);

		if (err)

			return err;

		err = read_poll_timeout(reset_control_status, status,

					status != 1, 0, 1000, false,

					priv->rstc);

	} else {

		err = reset_control_reset(priv->rstc);

	}



	return err;

}



static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv)

{

	/* delay timer when change the setting register */
@@ -189,13 +164,12 @@ static int rzg2l_wdt_restart(struct watchdog_device *wdev, 
			     unsigned long action, void *data)

{

	struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);

	int ret;



	clk_prepare_enable(priv->pclk);

	clk_prepare_enable(priv->osc_clk);



	if (priv->devtype == WDT_RZG2L) {

		int ret;



		ret = reset_control_deassert(priv->rstc);

		if (ret)

			return ret;
@@ -207,7 +181,9 @@ static int rzg2l_wdt_restart(struct watchdog_device *wdev, 
		rzg2l_wdt_write(priv, PEEN_FORCE, PEEN);

	} else {

		/* RZ/V2M doesn't have parity error registers */

		rzg2l_wdt_reset(priv);

		ret = reset_control_reset(priv->rstc);

		if (ret)

			return ret;



		wdev->timeout = 0;
@@ -299,13 +275,6 @@ static int rzg2l_wdt_probe(struct platform_device *pdev) 


	priv->devtype = (uintptr_t)of_device_get_match_data(dev);



	if (priv->devtype == WDT_RZV2M) {

		priv->minimum_assertion_period = RZV2M_A_NSEC +

			3 * F2CYCLE_NSEC(pclk_rate) + 5 *

			max(F2CYCLE_NSEC(priv->osc_clk_rate),

			    F2CYCLE_NSEC(pclk_rate));

	}



	pm_runtime_enable(&pdev->dev);



	priv->wdev.info = &rzg2l_wdt_ident;